Power MOSFETsActive

BSS138

Manufacturer: onsemi

Figures from the datasheet: onsemi BSS138/D, rev. Rev. 7, April 2024

onsemi BSS138 N-channel logic-level MOSFET in SOT-23 (CASE 318-08), G-S-D pinout; absolute VDSS limit 50 V and continuous ID limit 220 mA at TA = 25°C.

PackagesSOT-23
Official Datasheet (PDF)

Technical Overview

01

Technical Overview

The BSS138 is an industry-standard small-signal N-channel enhancement-mode logic-level field-effect transistor produced by onsemi (datasheet BSS138/D, Rev. 7, April 2024). Housed in an industry-standard surface-mount SOT-23 package (TO-236AB / CASE 318-08), the device features a G-S-D pinout: Pin 1 Gate (G), Pin 2 Source (S), and Pin 3 Drain (D). Absolute maximum ratings at TA = 25°C specify a drain-source breakdown voltage VDSS of 50V, continuous drain-gate voltage VDGR of 50V (RGS <= 1 MΩ), continuous gate-source voltage VGSS of ±20V (non-repetitive peak ±40V for tp < 50 µs), continuous drain current ID of 220mA, pulsed drain current IDM of 880mA, and total device dissipation PD of 360mW (derating 2.8 mW/°C above 25°C; thermal resistance junction-to-ambient RthetaJA = 350°C/W on minimum pad). Electrical characteristics guarantee minimum drain-source breakdown voltage BVDSS = 50V tested at VGS = 0V, ID = 250 µA. Gate threshold voltage VGS(th) spans 0.8V min, 1.3V typ, to 1.5V max at VDS = VGS, ID = 1.0 mA, representing the onset of channel conduction. Static drain-source on-resistance RDS(on) is guaranteed at 1.4 Ω typ, 3.5 Ω max at VGS = 10V, ID = 0.22 A, and 1.9 Ω typ, 6.0 Ω max at VGS = 4.5V, ID = 0.22 A. Switching speeds are rapid, with typical turn-on delay td(on) = 2.5 ns (20 ns max), rise time tr = 9 ns (20 ns max), turn-off delay td(off) = 20 ns (50 ns max), and fall time tf = 7 ns (20 ns max) under VDD = 30V, ID = 0.22 A, VGS = 10V, and RGEN = 50 Ω. Input capacitance Ciss is 27 pF typ (50 pF max) at VDS = 25V, VGS = 0V, f = 1.0 MHz. The integrated body diode specifies a maximum continuous forward source current IS of 0.22 A and forward voltage VSD of 0.8V typ, 1.4V max at VGS = 0V, IS = 0.22 A.

Package Pinout & Alternate Functions

Interactive package pinout and pin mapping for SOT-23-3.

Interactive pinout diagramTop

BSS138: SOT-23 package illustrationInteractive package pinout and pin mapping for SOT-23.1: G2: S3: D

Package illustration, not a dimensioned mechanical drawing.

3 / 3 pins
#Pin nameType5V TolerantAlternate functions / details
Gpassive—
Gate terminal (pin 1, bottom-left lead of SOT-23 / CASE 318-08; high-impedance gate input, absolute VGS limit ±20V continuous, ±40V non-repetitive peak for tp < 50 µs)
Spassive—
Source terminal (pin 2, bottom-right lead of SOT-23 / CASE 318-08; common reference terminal for gate and drain potentials)
Dpassive—
Drain terminal (pin 3, top-center lead of SOT-23 / CASE 318-08; absolute VDSS limit 50V, continuous ID limit 220 mA at TA = 25°C)

Key Specifications

Parametric attributes

ParameterMinTypicalMaxUnitTest condition
Drain-Source Breakdown Voltage(BVDSS)50——VVGS = 0 V, ID = 250 µA, TJ = 25°C
Gate-Threshold Voltage(VGS_th)0.81.31.5VVDS = VGS, ID = 1.0 mA, TJ = 25°C
Zero Gate Voltage Drain Current(IDSS)——0.5µAVDS = 50 V, VGS = 0 V, TJ = 25°C
Gate-Body Leakage Current(IGSS)——100nAVGS = ±20 V, VDS = 0 V, TJ = 25°C
Drain-Source On-Resistance at 10V(RDS_on_10V)—1.43.5ΩVGS = 10 V, ID = 0.22 A, TJ = 25°C
Drain-Source On-Resistance at 4.5V(RDS_on_4_5V)—1.96ΩVGS = 4.5 V, ID = 0.22 A, TJ = 25°C
Forward Transconductance(gFS)170350—mSVDS = 10 V, ID = 0.22 A, TJ = 25°C
Input Capacitance(Ciss)—2750pFVDS = 25 V, VGS = 0 V, f = 1.0 MHz, TJ = 25°C
Output Capacitance(Coss)—1125pFVDS = 25 V, VGS = 0 V, f = 1.0 MHz, TJ = 25°C
Reverse Transfer Capacitance(Crss)—48pFVDS = 25 V, VGS = 0 V, f = 1.0 MHz, TJ = 25°C
Turn-On Delay Time(td_on)—2.520nsVDD = 30 V, ID = 0.22 A, VGS = 10 V, RGEN = 50 Ω, TJ = 25°C
Rise Time(tr)—920nsVDD = 30 V, ID = 0.22 A, VGS = 10 V, RGEN = 50 Ω, TJ = 25°C
Turn-Off Delay Time(td_off)—2050nsVDD = 30 V, ID = 0.22 A, VGS = 10 V, RGEN = 50 Ω, TJ = 25°C
Fall Time(tf)—720nsVDD = 30 V, ID = 0.22 A, VGS = 10 V, RGEN = 50 Ω, TJ = 25°C
Absolute Maximum Drain-Source Voltage(VDSS)——50VTA = 25°C
Absolute Maximum Continuous Drain Current(ID_cont)——220mATA = 25°C
Absolute Maximum Pulsed Drain Current(IDM)——880mATA = 25°C
Absolute Maximum Total Device Dissipation(PD)——360mWTA = 25°C; derate 2.8 mW/°C above 25°C
Body Diode Forward Voltage(VSD)—0.81.4VVGS = 0 V, IS = 0.22 A, TJ = 25°C

Absolute Maximum Ratings

Storage temperature-55 – 150 °C
Thermal resistance θJA (SOT-23)350 °C/W

Hardware Engineering Gotchas

Real-world hardware caveats, PCB layout constraints and silicon errata to know before manufacturing.

Critical

Source Versus Drain Orientation in Bidirectional I2C Level Shifter Circuits

In classic bidirectional I2C logic level shifter circuits (NXP AN10441), the MOSFET source terminal must be connected to the lower-voltage supply rail domain (e.g., 3.3V) with its gate tied to the 3.3V supply, while the drain terminal faces the higher-voltage bus domain (e.g., 5V). Because the enhancement-mode MOSFET contains an intrinsic body diode directed from source to drain, reversing source and drain places the anode at the higher 5V rail and cathode at the 3.3V rail. This permanently forward-biases the internal body diode whenever the 3.3V side is lower, causing unconstrained current leakage from the 5V rail into the 3.3V rail and clamping the high-voltage bus down.

Mitigation

Orient the BSS138 strictly with Source (pin 2) on the lower-voltage side (VCC_low) and Drain (pin 3) on the higher-voltage side (VCC_high). Gate (pin 1) connects directly to VCC_low. Provide external pull-up resistors on both sides to establish correct quiescent high states.

Critical

Small-Signal On-Resistance (RDS(on) up to 6.0 Ω) Precludes Power Load Switching

The BSS138 is designed specifically for small-signal logic level shifting and high-speed digital switching, not power load switching. Datasheet BSS138/D specifies static on-resistance of up to 3.5 Ω at VGS = 10V and up to 6.0 Ω at VGS = 4.5V (at ID = 0.22 A). Passing 150 mA through a 6.0 Ω channel produces a 0.9V voltage drop across the transistor and generates 135 mW of power dissipation. In a tiny SOT-23 package with thermal resistance RthetaJA = 350°C/W on minimum pad, this raises the junction temperature by over 47°C above ambient, causing thermal stress.

Mitigation

Restrict BSS138 switching to low-current digital signals, communication lines, and pull-up networks (ID < 50 mA). For power switching, motor control, or relay driving above 100 mA, select a low-RDS(on) power MOSFET such as IRLZ44N, 2N7000, or a dedicated modern power TrenchFET.

Warning

Sub-3.3V Logic Drive and Lack of Guaranteed Low-Voltage Gate Overdrive

Although the gate threshold voltage VGS(th) is specified between 0.8V and 1.5V (tested at ID = 1.0 mA), the threshold represents only the initial onset of channel conduction. The onsemi BSS138 datasheet provides guaranteed RDS(on) specifications only at VGS = 10V (<= 3.5 Ω) and VGS = 4.5V (<= 6.0 Ω); it does not guarantee on-resistance at 1.8V, 2.5V, or 3.3V gate drive. When used to translate signals between 1.8V and 3.3V logic systems, gate overdrive (VGS - VGS(th)) can be as small as 0.3V on worst-case parts, leading to significantly higher channel resistance and slow signal rise times on capacitive I2C buses.

Mitigation

For 1.8V or 2.5V logic domains, calculate bus RC time constants assuming a higher effective channel resistance (~15–30 Ω). If rise times violate I2C fast-mode (400 kHz) bus specifications, reduce pull-up resistance values accordingly, or use dedicated sub-1.8V translator ICs (such as PCA9306 or TXS0102).

Warning

Parasitic Body Diode Conduction During Negative Voltage Ringing or Rail Sequencing

The integral body diode between source (anode) and drain (cathode) has a forward conduction voltage of 0.8V typ, 1.4V max. If bus lines experience inductive overshoot, ground bounce, or if the higher-voltage supply rail is unpowered while the lower-voltage side remains active, current can conduct parasitically through the body diode. In power-down scenarios where the 5V supply is collapsed to ground, pulling a 3.3V line low will not conduct, but raising it high may backfeed into the collapsed 5V bus through the pull-up and channel.

Mitigation

Verify power rail sequencing in multi-voltage embedded systems. Ensure supply decoupling capacitors discharge safely and avoid situations where signals are driven into unpowered IC pins. When driving inductive loads or long cables, add Schottky clamp diodes to suppress negative ground ringing.

Reference Circuits

BSS138 Bidirectional I2C 3.3V to 5V Level Shifter

Topology: Bidirectional N-channel MOSFET voltage level translator with gate clamped to 3.3V, source on 3.3V bus, and discrete pull-ups.

Inspect schematicOpen in Web CAD Editor

Official Documentation & Cited Datasheets

Primary semiconductor vendor datasheets, errata, and application notes.

DATASHEETonsemi

BSS138 N-Channel Logic Level Enhancement Mode Field Effect Transistor

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