BSS138 Bidirectional I2C 3.3V to 5V Level Shifter

The circuit operates as a two-channel bidirectional voltage level translator for the open-drain I2C serial bus, interfacing a lower-voltage system section (VDD1 = +3.3 V) with a higher-voltage section (VDD2 = +5.0 V). Each bus line (SDA and SCL) employs a single discrete N-channel enhancement-mode MOSFET (Q1 for SDA, Q2 for SCL). The gates of both MOSFETs are permanently connected to the lower supply voltage VDD1 (+3.3 V). The source terminals connect to the 3.3 V bus side, and the drain terminals connect to the 5.0 V bus side. Pull-up resistors R1 and R2 (10 kΩ) pull the 3.3 V lines to VDD1, while R3 and R4 (10 kΩ) pull the 5.0 V lines to VDD2. Decoupling capacitors C1 and C2 (100 nF X7R ceramic) provide low-impedance high-frequency bypass directly at each supply domain.

When no bus device (master or slave) is driving the bus, the open-drain lines on both sections are held HIGH by their respective pull-up resistors: the 3.3 V lines sit at +3.3 V and the 5.0 V lines sit at +5.0 V. For both transistors Q1 and Q2, the gate is at +3.3 V and the source is at +3.3 V, resulting in a gate-to-source voltage of exactly zero (VGS = VG - VS = 3.3V - 3.3V = 0 V). Because VGS is far below the threshold voltage (VGS(th) = 0.8\dots 1.5 V), the MOSFETs are completely pinched off in cutoff. The higher-voltage 5.0 V section is completely isolated from the lower-voltage 3.3 V section, preventing overvoltage stress or phantom leakage into 3.3 V microcontroller I/O pins.

When an active device on the 3.3 V section asserts a logic LOW, it pulls the source of the MOSFET down toward ground (VS ≈ 0 V). Because the gate remains clamped at +3.3 V, the gate-to-source voltage abruptly rises to VGS = 3.3V - 0V = 3.3 V, well above the maximum threshold voltage of 1.5 V. The MOSFET turns fully ON, providing a low-resistance conduction channel (RDS(on) ≤ 6.0 Ω). Current from the 5.0 V pull-up resistor flows through the conducting channel to ground via the 3.3 V pull-down driver, pulling the drain (5.0 V bus line) down to a matching logic LOW state (VOL2 = VOL1 + Ipull-up · RDS(on) ≤ 0.4 V).

When an active device on the 5.0 V section asserts a logic LOW, it pulls the drain of the MOSFET down toward ground. Initially, the MOSFET channel is non-conducting. However, the intrinsic body diode of the N-channel MOSFET is oriented with its anode at the source (3.3 V side) and its cathode at the drain (5.0 V side). As the drain voltage drops below approximately 2.6 V, the body diode becomes forward-biased and begins conducting, pulling the source down via diode forward drop (VS = VD + VSD ≈ 0.7 V). As the source voltage drops below 3.3V - VGS(th) ≈ 1.8 V, VGS exceeds the threshold voltage, and the inversion channel turns ON. Once the channel conducts, it bypasses the forward diode drop, pulling the 3.3 V line cleanly down to a true logic LOW state matching the 5.0 V driver level.

When the active pull-down driver on either side releases the bus, both sides begin rising toward their respective supply rails. Initially, while the line voltage is below VDD1 - VGS(th), the conducting MOSFET keeps both sides tied together, rising in unison. Once the lower-voltage line exceeds VDD1 - VGS(th) ≈ 1.8 V, VGS falls below the threshold, and the MOSFET turns OFF. From that instant forward, the two bus sections rise independently: the 3.3 V section charges through R1/R2 with time constant \tau1 = Rp · Cb1, and the 5.0 V section charges through R3/R4 with time constant \tau2 = Rp · Cb2. This allows high-voltage bus capacitance to be electrically decoupled from the low-voltage bus section, improving overall signal integrity.