MCU Interfaces
Dual-transistor auto-download circuit driving ESP32 EN and IO0 boot strapping pins via USB-to-UART DTR and RTS lines.
Circuit overview
Click any component in the schematic above to inspect its electrical ratings, function, and connections.
This is the "auto program" block of the Espressif ESP32-DevKitC V4 schematic, redrawn with its EN delay network and the BOOT and EN buttons. The ESP32 starts its serial bootloader when IO0 is low at the moment it comes out of reset. A USB-to-UART bridge such as the CP2102N on the DevKitC or a CH340G has two spare modem control outputs, DTR and RTS, and flashing tools toggle them to drive EN and IO0. The two NPN transistors are cross-coupled so that each one conducts only when its two control lines differ: when DTR and RTS are both high or both low nothing happens, so a terminal program that sets both lines together does not reset the chip. The reference board uses SS8050 transistors; the general-purpose 2N3904 drawn here does the same job at these currents. The EN pull-up and capacitor follow the 10 kΩ and 1 µF that Espressif recommends; the DevKitC V4 fits 0.1 µF. GPIO0 has an internal weak pull-up, so the circuit needs no resistor on IO0.
| Operating Logic Level | 3.3 V (VDD33 on the DevKitC V4) |
|---|---|
| Control Truth Table (pin levels) | DTR 1, RTS 0 → EN 0; DTR 0, RTS 1 → IO0 0; equal levels → EN 1, IO0 1 (DevKitC V4 schematic) |
| Reset Condition | CHIP_PU below 0.6 V for at least 50 µs (Espressif Hardware Design Guidelines) |
| EN Delay Network | 10 kΩ and 1 µF recommended by Espressif, τ = 10 ms (calculated); DevKitC V4 fits 0.1 µF |
| Bootloader Condition | IO0 low at reset release; GPIO2 low or unconnected (esptool documentation) |
| Transistors | SS8050 on the DevKitC V4; 2N3904 drawn here |
| Base Current | ≈ 0.26 mA per transistor with 10 kΩ base resistors (calculated, VBE ≈ 0.7 V assumed) |
DTR and RTS are active-low outputs: when the software asserts a line, the pin goes to 0 V; when it releases the line, the pin returns to 3.3 V. Everything below is described in pin levels, as in the truth table printed on the DevKitC V4 schematic.
Q1 has its base on DTR through R1 and its emitter on RTS; its collector pulls EN. Q2 is the mirror image: base on RTS through R2, emitter on DTR, collector on IO0. A transistor conducts only when its base side is high and its emitter side is low:
DTR = 1, RTS = 1: both transistors off, EN = 1, IO0 = 1.
DTR = 0, RTS = 0: both transistors off, EN = 1, IO0 = 1.
DTR = 1, RTS = 0: Q1 on, EN = 0 (chip in reset), IO0 = 1.
DTR = 0, RTS = 1: Q2 on, EN = 1, IO0 = 0.
Because equal levels switch nothing, opening a port that asserts both lines together does not reset the chip. When a transistor is off with its emitter high and its base low, its base-emitter junction is reverse-biased by 3.3 V, well inside the 6 V minimum V(BR)EBO of the 2N3904.
esptool first sets DTR = 1, RTS = 0. Q1 saturates, pulls EN to ground and discharges C1. The ESP32 resets when CHIP_PU stays below 0.6 V for at least 50 µs; esptool holds this state for 100 ms. With R1 = 10 kΩ the base current of Q1 is about:
IB = (VDTR - VBE) / (R1) ≈ (3.3 V - 0.7 V) / (10 kΩ) = 0.26 mAwhich saturates the transistor against the 0.33 mA that R3 supplies.
esptool then sets DTR = 0 and RTS = 1 in two back-to-back calls. Between them both lines are briefly low and both transistors off; C1 slows the rise of EN across that gap, so the chip is still held in reset when Q2 turns on and pulls IO0 low. EN then rises through R3 into C1:
\tau = R3 × C1 = 10 kΩ × 1\,µF = 10 msThe chip samples its strapping pins as it comes out of reset. Finding IO0 low, it starts the serial bootloader instead of the program in flash. GPIO2 must also be low or unconnected for the bootloader to start.
After 50 ms esptool releases DTR, so both lines are high, both transistors are off and IO0 returns high through its internal pull-up. The bootloader keeps running and the upload continues over TXD0 and RXD0. To run the new firmware, esptool pulses RTS alone (DTR = 1, RTS = 0) for a plain hardware reset with IO0 high.
Time constant of the rise of EN after Q1 or SW2 releases it.
| Symbol | Parameter | Typical value |
|---|---|---|
| R3 | EN pull-up resistor | 10kΩ |
| C1 | EN delay capacitor | 1µF |
| τ | Time constant (calculated) | 10ms |
EN reaches 63% of the supply after one time constant and about 99% after five (50 ms with the values drawn).
| Symbol | Parameter | Typical value |
|---|---|---|
| VDD | Supply voltage | 3.3V |
| τ | Time constant | 10ms |
Base current of the conducting transistor when its control line is high and the other is low.
| Symbol | Parameter | Typical value |
|---|---|---|
| VDD | Control line high level | 3.3V |
| VBE | Base-emitter voltage (assumed) | 0.7V |
| R1 | Base resistor | 10kΩ |
| IB | Base current (calculated) | 0.26mA |
Every part needed to build this circuit. Select a reference designator to inspect it on the schematic.
| RefDes | Component | Value / rating | Package | Role in circuit | Reference |
|---|---|---|---|---|---|
| NPN Small-Signal Transistor SS8050-G on the DevKitC V4. Any small NPN switch works at these currents. | 2N3904 | TO-92 | Pulls EN low | NPN Small-Signal Transistor pinout & datasheet | |
| NPN Small-Signal Transistor SS8050-G on the DevKitC V4. | 2N3904 | TO-92 | Pulls IO0 low | NPN Small-Signal Transistor pinout & datasheet | |
| Resistor R21 on the DevKitC V4. | 10kΩ | 0603 / 0805 / axial | Q1 base resistor | — | |
| Resistor R22 on the DevKitC V4. | 10kΩ | 0603 / 0805 / axial | Q2 base resistor | — | |
| Resistor R11 on the DevKitC V4. | 10kΩ | 0603 / 0805 / axial | EN pull-up | — | |
| Ceramic Capacitor Espressif-recommended value. The DevKitC V4 fits 0.1 µF (C9), plus 0.1 µF across the EN button (C14). | 1µF | 0603 / 0805 | EN delay | — | |
| Tactile Switch The DevKitC V4 adds 0.1 µF across it (C15). | BOOT | SMD / THT | Manual IO0 low | — | |
| Tactile Switch | EN | SMD / THT | Manual reset | — |
Traps found in real builds, with the fix for each.
Without a capacitor from EN to GND, or with a very small one, automatic reset is unreliable and esptool may fail to connect to the chip, most often on Windows.
Fit 1 µF to 10 µF from EN to GND, as the esptool documentation recommends; 1 µF with 10 kΩ matches the Espressif hardware design guidelines.
Some terminal programs and drivers set RTS or DTR on their own when they open the port, and RTS/CTS hardware flow control drives RTS. Depending on the levels the board resets, or stays in reset or in the bootloader. On Linux an idle port may assert RTS by default.
Disable RTS/CTS hardware flow control in the terminal program. On Linux, clear HUPCL on the port (stty -F /dev/ttyUSB0 -hupcl) as the esptool documentation describes.
The ESP32 enters the serial bootloader only when GPIO2 is low or unconnected as well as IO0 low. A pull-up or another circuit holding GPIO2 high keeps the auto-reset from working even though the transistors switch correctly.
Leave GPIO2 unconnected or make sure it is low at reset; do not put a pull-up on it.
A large capacitor on IO0 keeps the pin low for a while after power-up, and the chip may start the bootloader instead of its program.
Do not add high-value capacitors to IO0, as the Espressif hardware design guidelines warn; the internal weak pull-up is the only pull-up this circuit relies on.
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