Bipolar TransistorsObsolete

2N3904

Manufacturer: onsemi

Figures from the datasheet: onsemi 2N3903/D, rev. Rev. 9, August 2021

General-purpose small-signal NPN silicon bipolar junction transistor in a TO-92 package with E-B-C pinout, featuring 40V VCEO and 200mA IC absolute maximum ratings.

PackagesTO-92
Official Datasheet (PDF)

Technical Overview

01

Technical Overview

The onsemi 2N3904 is a small-signal NPN silicon bipolar junction transistor in the through-hole TO-92 package (Case 29, Style 1) with pins 1–2–3 assigned emitter–base–collector. The datasheet (2N3903/D, August 2021, Rev. 9) lists absolute maximum ratings of VCEO = 40 V, continuous IC = 200 mA, and PD = 625 mW at TA = 25°C, derated by 5.0 mW/°C above 25°C. These stress ratings are not unconditional working capabilities and must be observed together with junction temperature and actual thermal conditions. TJ = −55 to +150°C is a junction-temperature range, not an ambient operating range. The listed thermal resistances, 200°C/W junction-to-ambient and 83.3°C/W junction-to-case, are maximum values. Separately, the measured breakdown voltage V(BR)CEO has a minimum of 40 V at IC = 1.0 mA and IB = 0. At TA = 25°C, hFE is specified as 100–300 at IC = 10 mA and VCE = 1.0 V, and VCE(sat) is at most 0.2 V at IC = 10 mA and IB = 1.0 mA; these breakdown/gain/saturation rows carry the applicable pulse-test qualification of pulse width ≤300 µs and duty cycle ≤2%. The current-gain bandwidth product fT is at least 300 MHz at IC = 10 mA, VCE = 20 V and measurement frequency f = 100 MHz (TA = 25°C). See the conditioned parametric rows rather than treating gain or saturation limits as independent of current, temperature or base drive.

Package Pinout & Alternate Functions

Interactive package pinout and pin mapping for TO-92-3.

Interactive pinout diagramFront

2N3904: TO-92 package illustrationInteractive package pinout and pin mapping for TO-92.1: E2: B3: C

Package illustration, not a dimensioned mechanical drawing.

3 / 3 pins
#Pin nameType5V TolerantAlternate functions / details
Epassive—
Emitter terminal (pin 1, left lead with flat face forward and leads downward)
Binput onlyNo
Base control terminal (pin 2, center lead; requires external base-current limiting resistor)
Cpassive—
Collector terminal (pin 3, right lead with flat face forward and leads downward)

Key Specifications

Parametric attributes

ParameterMinTypicalMaxUnitTest condition
Collector-Emitter Breakdown Voltage(V(BR)CEO)40——VIC = 1.0 mA, IB = 0, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%)
Collector-Base Breakdown Voltage(V(BR)CBO)60——VIC = 10 µA, IE = 0, TA = 25°C
Emitter-Base Breakdown Voltage(V(BR)EBO)6——VIE = 10 µA, IC = 0, TA = 25°C
Continuous Collector Current(IC)——200mAAbsolute maximum continuous collector current (Maximum Ratings, p. 1); observe power dissipation and junction-temperature limits simultaneously.
DC Current Gain at 10mA(hFE_10mA)100—300ratioIC = 10 mA, VCE = 1.0 V, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%)
DC Current Gain at 1mA(hFE_1mA)70——ratioIC = 1.0 mA, VCE = 1.0 V, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%)
DC Current Gain at 50mA(hFE_50mA)60——ratioIC = 50 mA, VCE = 1.0 V, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%)
Collector-Emitter Saturation Voltage at 10mA(VCE_sat_10mA)——0.2VIC = 10 mA, IB = 1.0 mA, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%)
Collector-Emitter Saturation Voltage at 50mA(VCE_sat_50mA)——0.3VIC = 50 mA, IB = 5.0 mA, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%)
Base-Emitter Saturation Voltage(VBE_sat)0.65—0.85VIC = 10 mA, IB = 1.0 mA, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%)
Current-Gain Bandwidth Product(fT)300——MHzIC = 10 mA, VCE = 20 V, f = 100 MHz, TA = 25°C
Collector Output Capacitance(Cobo)——4pFVCB = 5.0 V, f = 1.0 MHz, IE = 0, TA = 25°C
Emitter Input Capacitance(Cibo)——8pFVEB = 0.5 V, f = 1.0 MHz, IC = 0, TA = 25°C
Noise Figure(NF)——5dBIC = 100 µA, VCE = 5.0 V, RS = 1.0 kΩ, f = 1.0 kHz, TA = 25°C
Collector-Emitter Voltage Absolute Maximum(VCEO)——40VMaximum Ratings, p. 1; stress rating, distinct from the V(BR)CEO minimum measured under its stated test conditions.
Emitter-Base Voltage Absolute Maximum(VEBO)——6VMaximum Ratings, p. 1; reverse emitter-base stress rating, distinct from the V(BR)EBO minimum measured under its stated test conditions.
Junction Temperature Range(TJ)-55—150°COperating junction temperature, Maximum Ratings, p. 1; not an ambient operating-temperature rating.

Absolute Maximum Ratings

Storage temperature-55 – 150 °C
Thermal resistance θJA (TO-92)200 °C/W
Thermal resistance θJC (TO-92)83.3 °C/W

Hardware Engineering Gotchas

Real-world hardware caveats, PCB layout constraints and silicon errata to know before manufacturing.

Critical

Verify the Exact TO-92 Emitter–Base–Collector Pinout

With the flat face of the onsemi TO-92 package facing the viewer and leads downward, pins 1–2–3 are emitter–base–collector (E-B-C). Other part numbers or manufacturers may use different lead arrangements. Swapping emitter and collector can cause incorrect circuit operation; depending on the bias conditions, reverse-active operation may occur with different gain and voltage limits. Verify the exact part and package drawing rather than assuming another transistor shares this pinout.

Mitigation

Always verify physical pin arrangement against the manufacturer datasheet and PCB silkscreen before assembly. Ensure the emitter, base, and collector match the schematic symbol connections.

Critical

Reverse Emitter–Base Stress in Cross-Coupled Astables

The datasheet lists VEBO = 6.0 V as the absolute maximum reverse emitter-base voltage (p. 1). Separately, V(BR)EBO is specified as at least 6.0 V at IE = 10 µA, IC = 0 and TA = 25°C (p. 2); the breakdown test is not a recommended operating condition. In a cross-coupled astable with grounded emitters, a falling collector can capacitively pull the opposite base negative. For an idealized instantaneous transition with capacitor voltage unchanged, VB(after) = VB(before) + VC(after) − VC(before). Thus the base voltage after the step includes its pre-switch base voltage; the collector step alone is not the final reverse VBE. Actual collector levels depend on load voltage drops, transistor drive and circuit state. Evaluate the worst-case reverse VBE in the specific circuit against the absolute VEBO limit; there is no universal supply-voltage threshold of 5–6 V derived from this datasheet. Excessive reverse stress may cause breakdown, degrade gain or alter timing.

Mitigation

Evaluate a reverse-parallel base-emitter clamp (cathode to base, anode to emitter/ground) or an alternative topology when the actual circuit analysis identifies excessive reverse stress. Check the clamp current, timing paths, startup and component voltage limits in the resulting circuit. A clamp or series-base diode arrangement is a design change requiring verification, not an automatically validated drop-in remedy.

Warning

BJT Base Current Drive Requirement for Saturation vs Active Gain

Active-region hFE does not guarantee the tabulated VCE(sat) limits. The onsemi saturation tests use forced beta IC / IB = 10: IC = 10 mA with IB = 1.0 mA gives VCE(sat) ≤0.2 V, and IC = 50 mA with IB = 5.0 mA gives VCE(sat) ≤0.3 V, at TA = 25°C with pulse width ≤300 µs and duty cycle ≤2%. These limits apply to the stated test conditions. Selecting base current solely from active-region hFE can provide insufficient drive for the intended load and leave a higher collector-emitter voltage and greater dissipation; the actual operating region depends on the circuit load line and drive.

Mitigation

Size the base drive for the actual collector load and verify the relevant saturation, voltage, temperature and pulse conditions. The tabulated tests use IC / IB = 10; they do not establish a universal guaranteed forced-beta range of 10–20. Check whether the driver can source the required base current and remove base charge during turn-off, within its own voltage and current limits. If suitable base drive is unavailable, evaluate a MOSFET or buffer against the actual circuit requirements rather than relying on a logic-level label alone.

Reference Circuits

ESP32 Auto-Reset and Boot Circuit (DTR/RTS)

Topology: Q1 and Q2: cross-coupled NPN switches that pull EN and IO0 low

Inspect schematicOpen in Web CAD Editor

Official Documentation & Cited Datasheets

Primary semiconductor vendor datasheets, errata, and application notes.

DATASHEETonsemi

2N3903, 2N3904 General Purpose Transistors NPN Silicon

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