Manufacturer: onsemi
Figures from the datasheet: onsemi 2N3906/D, rev. Rev. 4, February 2010
General-purpose small-signal PNP silicon bipolar junction transistor in a TO-92 package with E-B-C pinout, featuring 40V VCEO and 200mA IC absolute maximum ratings.
The 2N3906 is a classic small-signal PNP silicon bipolar junction transistor (BJT) manufactured by onsemi (Publication Order Number 2N3906/D, Rev. 4, February 2010). Housed in the through-hole TO-92 package (Case 29-11, Issue AM, Style 1) with an E-B-C lead configuration, it serves as the foundational complementary counterpart to the NPN 2N3904.
In standard forward-active PNP operation, base and collector voltages are negative relative to the emitter (VBE < 0, VCE < 0). Datasheet specification tables list positive voltage magnitudes (|VCE|, |VBE|, |V(BR)|).
TA = 25°C)VCEO): 40 VVCBO): 40 VVEBO): 5.0 VIC): 200 mAPD): 625 mW at TA = 25°C (derated at 5.0 mW/°C above 25°C); explicit rating of 250 mW at TA = 60°C; 1.5 W at TC = 25°C (derated at 12 mW/°C)TJ): -55°C to +150°CθJA = 200°C/W junction-to-ambient and θJC = 83.3°C/W junction-to-case (source maxima)TA = 25°C)V(BR)CEO ≥ 40 V (IC = 1.0 mA), V(BR)CBO ≥ 40 V (IC = 10 µA), V(BR)EBO ≥ 5.0 V (IE = 10 µA)hFE): 100 to 300 at IC = 10 mA and |VCE| = 1.0 V|VCE(sat)|): ≤ 0.25 V at IC = 10 mA and IB = 1.0 mAfT): ≥ 250 MHz at IC = 10 mA, |VCE| = 20 V, and f = 100 MHzInteractive package pinout and pin mapping for TO-92-3.
Package illustration, not a dimensioned mechanical drawing.
| # | Pin name | Type | 5V Tolerant | Alternate functions / details |
|---|---|---|---|---|
| E | passive | — | Emitter terminal (pin 1, left lead with flat face forward and leads downward) | |
| B | input only | No | Base control terminal (pin 2, center lead; requires external base-current limiting resistor) | |
| C | passive | — | Collector terminal (pin 3, right lead with flat face forward and leads downward) |
| Parameter | Min | Typical | Max | Unit | Test condition |
|---|---|---|---|---|---|
| Collector-Emitter Breakdown Voltage V(BR)CEO(V(BR)CEO) | 40 | — | — | V | IC = 1.0 mA, IB = 0, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%) |
| Collector-Base Breakdown Voltage V(BR)CBO(V(BR)CBO) | 40 | — | — | V | IC = 10 µA, IE = 0, TA = 25°C |
| Emitter-Base Breakdown Voltage V(BR)EBO(V(BR)EBO) | 5 | — | — | V | IE = 10 µA, IC = 0, TA = 25°C |
| Continuous Collector Current(IC_max) | — | — | 200 | mA | Continuous rating (simultaneous PD and TJ constraints apply) |
| DC Current Gain hFE at 10mA(hFE_10mA) | 100 | — | 300 | ratio | IC = 10 mA, |VCE| = 1.0 V, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%) |
| DC Current Gain hFE at 1mA(hFE_1mA) | 80 | — | — | ratio | IC = 1.0 mA, |VCE| = 1.0 V, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%) |
| DC Current Gain hFE at 50mA(hFE_50mA) | 60 | — | — | ratio | IC = 50 mA, |VCE| = 1.0 V, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%) |
| Collector-Emitter Saturation Voltage |VCE(sat)| at 10mA(VCE_sat_10mA) | — | — | 0.25 | V | IC = 10 mA, IB = 1.0 mA, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%) |
| Collector-Emitter Saturation Voltage |VCE(sat)| at 50mA(VCE_sat_50mA) | — | — | 0.4 | V | IC = 50 mA, IB = 5.0 mA, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%) |
| Base-Emitter Saturation Voltage |VBE(sat)| at 10mA(VBE_sat_10mA) | 0.65 | — | 0.85 | V | IC = 10 mA, IB = 1.0 mA, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%) |
| Base-Emitter Saturation Voltage |VBE(sat)| at 50mA(VBE_sat_50mA) | — | — | 0.95 | V | IC = 50 mA, IB = 5.0 mA, TA = 25°C (Pulse Test: tp <= 300 µs, duty <= 2.0%) |
| Current-Gain Bandwidth Product(fT) | 250 | — | — | MHz | IC = 10 mA, |VCE| = 20 V, f = 100 MHz, TA = 25°C |
| Collector Output Capacitance(Cobo) | — | — | 4.5 | pF | VCB = 5.0 V, f = 1.0 MHz, IE = 0, TA = 25°C |
| Emitter Input Capacitance(Cibo) | — | — | 10 | pF | VEB = 0.5 V, f = 1.0 MHz, IC = 0, TA = 25°C |
| Noise Figure(NF) | — | — | 4 | dB | IC = 100 µA, |VCE| = 5.0 V, RS = 1.0 kΩ, f = 1.0 kHz, TA = 25°C |
| Collector-Emitter Voltage Absolute Maximum (Magnitude)(VCEO) | — | — | 40 | V | Maximum Ratings, p. 1; stress magnitude, distinct from the V(BR)CEO minimum under its stated measurement conditions. |
| Reverse Emitter-Base Voltage Absolute Maximum (Magnitude)(VEBO) | — | — | 5 | V | Maximum Ratings, p. 1; reverse emitter-base stress magnitude, distinct from the V(BR)EBO minimum under its stated measurement conditions. |
| Junction Temperature Range(TJ) | -55 | — | 150 | °C | Operating junction temperature, Maximum Ratings, p. 1; not an ambient operating-temperature range. |
| Storage temperature | -55 – 150 °C |
| Thermal resistance θJA (TO-92) | 200 °C/W |
| Thermal resistance θJC (TO-92) | 83.3 °C/W |
Real-world hardware caveats, PCB layout constraints and silicon errata to know before manufacturing.
VEBO = 5.0V)The base-emitter junction has an absolute maximum reverse rating of VEBO = 5.0V. Separately, measured breakdown V(BR)EBO is at least 5.0V at IE = 10 µA, IC = 0 and TA = 25°C; this breakdown test is not a recommended operating condition. In cross-coupled astable multivibrators or capacitive switching circuits, coupling transients can reverse-bias the base-emitter junction (driving the base positive relative to the emitter, VBE = VB - VE > 0). Exceeding the reverse stress limit can damage the device or affect reliability.
Evaluate actual transient peak reverse VBE during circuit operation. If reverse transients can approach or exceed 5.0V, incorporate an anti-parallel clamp diode across the base-emitter junction (such as a 1N4148 with anode to base and cathode to emitter for PNP) or an isolated series base blocking diode, verifying that the clamping solution does not disrupt required timing, start-up conditions, or forward drive.
Looking at the flat face of the TO-92 package with leads pointing downward, the onsemi 2N3906 pinout is Pin 1 = Emitter, Pin 2 = Base, Pin 3 = Collector (E-B-C, Case 29-11, Style 1). Other small-signal transistors in TO-92 packages employ different pin configurations (such as C-B-E or E-C-B). Installing the device with transposed leads leads to incorrect circuit operation and potentially reverse-active behavior with severely degraded current gain, altered saturation voltage, and reduced breakdown capability.
Always verify the physical lead arrangement against the manufacturer datasheet (onsemi 2N3906/D Style 1) and PCB silkscreen prior to soldering or breadboarding. Never assume TO-92 transistors share interchangeable pinouts across different part numbers or manufacturers.
For forward-active and saturated operation of a PNP transistor, the base terminal must be pulled lower than the emitter (VBE = VB - VE < 0). The onsemi datasheet characterizes collector-emitter saturation voltage magnitudes (|VCE(sat)| <= 0.25V at IC = 10mA, IB = 1.0mA; and <= 0.4V at IC = 50mA, IB = 5.0mA) at a forced beta of IC / IB = 10 under pulsed test conditions (tp <= 300 µs, duty <= 2.0%, TA = 25°C). Active-region hFE alone does not guarantee these saturation limits. Inadequate base drive can leave a higher collector-emitter voltage and greater dissipation; the actual operating region depends on the load and drive. Additionally, when high-side switching from a positive supply rail higher than the control logic rail, driving the base directly from a logic output can forward-bias the driver's high-side protection structure to the lower logic supply.
Size base drive based on load current, switching speed, and required saturation voltage using the applicable conditioned datasheet limits; typical curves do not establish universal guaranteed bounds. Verify that the driver can sink the required turn-on base current and remove stored base charge during turn-off within its own voltage and current limits. When switching a positive supply rail higher than the logic level (e.g. 12V supply with 3.3V or 5V logic), check driver off-state voltage limits and use an appropriately rated level shifter (such as an NPN transistor or open-drain stage with a base-to-emitter pull-up resistor referenced to the positive supply rail) to ensure complete turn-off.
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