Power MOSFETsActive

2N7000

Manufacturer: onsemi

Figures from the datasheet: onsemi NDS7002A/D, rev. Rev. 11, March 2025

onsemi 2N7000 N-channel MOSFET in TO-92 (CASE 135AN), S-G-D pinout; absolute VDSS limit 60 V and continuous ID limit 200 mA at TC = 25°C.

PackagesTO-92
Official Datasheet (PDF)

Technical Overview

01

Technical Overview

The 2N7000 is an industry-standard small-signal N-channel enhancement-mode field-effect transistor produced by onsemi (datasheet NDS7002A/D, Rev. 11, March 2025). Fabricated using proprietary high cell density DMOS technology, the bulk 2N7000 is housed in a through-hole TO-92 package (CASE 135AN) with an S-G-D pinout (Pin 1 Source, Pin 2 Gate, Pin 3 Drain). Absolute maximum ratings at TC = 25°C specify a drain-source voltage of 60V, continuous drain-gate voltage of 60V (RGS <= 1 MΩ), continuous gate-source voltage of ±20V (non-repetitive peak ±40V for tp < 50 ms), continuous drain current of 200mA, pulsed drain current of 500mA, and total device dissipation of 400mW (derating 3.2 mW/°C above 25°C; RthetaJA = 312.5°C/W). Electrical characteristics guarantee minimum drain-source breakdown voltage BVDSS = 60V tested at VGS = 0V, ID = 10 µA. Gate threshold voltage VGS(th) spans 0.8V min, 2.1V typ, to 3.0V max at VDS = VGS, ID = 1.0 mA, representing the onset of channel conduction rather than low on-resistance enhancement. Static on-resistance RDS(on) is specified at 1.2 Ω typ, 5.0 Ω max at VGS = 10V, ID = 500 mA, and 1.8 Ω typ, 5.3 Ω max at VGS = 4.5V, ID = 75 mA. Switching times ton and toff are guaranteed at <= 10 ns max under specified test circuit conditions (VDD = 15V, RL = 25 Ω, ID = 500 mA, VGS = 10V, RGEN = 25 Ω). Input capacitance Ciss is 20 pF typ, 50 pF max at VDS = 25V, VGS = 0V, f = 1.0 MHz. Onsemi publishes no guaranteed body diode forward voltage or reverse recovery rows for the 2N7000 variant.

Package Pinout & Alternate Functions

Interactive package pinout and pin mapping for TO-92-3.

Interactive pinout diagramFront

2N7000: TO-92 package illustrationInteractive package pinout and pin mapping for TO-92.1: S2: G3: D

Package illustration, not a dimensioned mechanical drawing.

3 / 3 pins
#Pin nameType5V TolerantAlternate functions / details
Spassive—
Source terminal (pin 1, CASE 135AN inline lead 1; p. 1 & p. 8 lead 1 Source)
Gpassive—
Gate terminal (pin 2, CASE 135AN inline lead 2; high-impedance gate input, VGS(th) 0.8V min, 2.1V typ, 3.0V max at 1 mA)
Dpassive—
Drain terminal (pin 3, CASE 135AN inline lead 3; p. 1 & p. 8 lead 3 Drain)

Key Specifications

Parametric attributes

ParameterMinTypicalMaxUnitTest condition
Drain-Source Breakdown Voltage(BVDSS)60——VVGS = 0 V, ID = 10 µA, TC = 25°C
Gate-Threshold Voltage(VGS_th)0.82.13VVDS = VGS, ID = 1.0 mA, TC = 25°C
Gate-Body Leakage Current Magnitude(IGSS)——10nAVDS = 0 V, VGS = +15 V (IGSSF) or -15 V (IGSSR), TC = 25°C; absolute magnitude of the signed +10/-10 nA limits
Zero Gate Voltage Drain Current(IDSS)——1µAVDS = 48 V, VGS = 0 V, TC = 25°C
Absolute Maximum Continuous Drain Current(ID_cont)——200mATC = 25°C
Absolute Maximum Pulsed Drain Current(IDM)——500mATC = 25°C
Drain-Source On-Resistance at 10V(RDS_on_10V)—1.25ΩVGS = 10 V, ID = 500 mA, TC = 25°C
Drain-Source On-Resistance at 4.5V(RDS_on_4_5V)—1.85.3ΩVGS = 4.5 V, ID = 75 mA, TC = 25°C
Forward Transconductance(gfs)100320—mSVDS = 10 V, ID = 200 mA, TC = 25°C
Input Capacitance(Ciss)—2050pFVDS = 25 V, VGS = 0 V, f = 1.0 MHz, TC = 25°C
Output Capacitance(Coss)—1125pFVDS = 25 V, VGS = 0 V, f = 1.0 MHz, TC = 25°C
Reverse Transfer Capacitance(Crss)—4.05pFVDS = 25 V, VGS = 0 V, f = 1.0 MHz, TC = 25°C
Turn-On Time(ton)——10nsVDD = 15 V, RL = 25 Ω, ID = 500 mA, VGS = 10 V, RGEN = 25 Ω, TC = 25°C
Turn-Off Time(toff)——10nsVDD = 15 V, RL = 25 Ω, ID = 500 mA, VGS = 10 V, RGEN = 25 Ω, TC = 25°C
Absolute Maximum Drain-Source Voltage(VDSS)——60VAbsolute maximum stress rating; TC = 25°C unless otherwise noted
Absolute Maximum Total Device Dissipation(PD)——400mWTC = 25°C; derate 3.2 mW/°C above 25°C (datasheet absolute maximum table)
Absolute Maximum Junction Temperature Range(TJ)-55—150°CAbsolute maximum junction-temperature limits, not an ambient operating range

Absolute Maximum Ratings

Storage temperature-55 – 150 °C
Thermal resistance θJA (TO-92)312.5 °C/W

Hardware Engineering Gotchas

Real-world hardware caveats, PCB layout constraints and silicon errata to know before manufacturing.

Critical

Gate Threshold Voltage Spread (0.8V–3.0V) and Direct 3.3V Logic Drive Limitations

The 2N7000 specifies a wide gate-source threshold spread of VGS(th) = 0.8V min, 2.1V typ, and 3.0V max tested at VDS = VGS, ID = 1.0 mA (TC = 25°C). This threshold indicates only the initial onset of channel conduction (1 mA) and does not guarantee low on-resistance ohmic conduction. When driven directly by a 3.3V microcontroller GPIO, devices with a threshold near the 3.0V upper limit experience minimal gate overdrive (VGS - VGS(th) ~ 0.3V). Datasheet NDS7002A/D specifies no guaranteed RDS(on) limit at 3.3V; on-resistance is guaranteed only at VGS = 4.5V (<= 5.3 Ω at 75 mA) and VGS = 10V (<= 5.0 Ω at 500 mA). Driving loads under marginal gate voltage can cause high channel resistance, severe voltage drop, and excess thermal dissipation.

Mitigation

Verify source-relative VGS across the threshold spread. For 3.3V or lower logic, choose a MOSFET with guaranteed RDS(on) at the actual drive voltage, or use a suitable gate driver. Check its minimum and maximum output VGS, including transients, against the selected on-resistance test conditions and the ±20V continuous gate-source absolute maximum; a driver supply voltage alone does not establish safe gate drive.

Critical

Characterization Test Conditions Versus Absolute Maximum Continuous Drain Current

In datasheet NDS7002A/D, electrical on-state resistance (RDS(on) <= 5.0 Ω) and switching times (ton, toff <= 10 ns) are characterized with test currents of ID = 500 mA at VGS = 10V. This 500 mA characterization test point must not be interpreted as permission for continuous operation. The 2N7000 on-resistance and switching rows do not specify pulse width or duty cycle. The absolute maximum continuous drain current rating for the bulk 2N7000 is 200 mA at TC = 25°C (with pulsed maximum IDM = 500 mA). Continuous operation at 500 mA violates absolute maximum ratings and may damage the device or affect reliability.

Mitigation

Treat 200 mA at TC = 25°C as an absolute maximum stress limit, not a recommended operating current. Select a lower operating current and check device dissipation and junction temperature for the actual thermal environment; the datasheet lists RthetaJA = 312.5°C/W and PD = 400 mW at TC = 25°C, derated by 3.2 mW/°C above 25°C.

Warning

Absence of Guaranteed Body Diode Specifications and Inductive Clamping Precautions

Datasheet NDS7002A/D provides guaranteed continuous forward current (IS), pulsed forward current (ISM), and forward voltage (VSD) specifications only for surface-mount variants (2N7002 and NDS7002A); it defines no guaranteed body diode limits for the through-hole 2N7000. In low-side switching circuits driving inductive loads (relays, solenoids, coils), turning off the MOSFET causes the inductor to pull the drain node positively above the supply rail, reverse-biasing the internal body diode. The internal diode cannot clamp this positive flyback transient, leaving the MOSFET vulnerable to destructive overvoltage breakdown beyond the 60V VDSS absolute maximum stress limit.

Mitigation

Provide an external flyback diode across the inductive load (cathode to the positive supply, anode to the MOSFET drain), or a suitably selected transient suppressor. Select its current, reverse-voltage, pulse-energy, and recovery ratings for the actual load and switching conditions; a generic diode part number alone does not establish suitability.

Official Documentation & Cited Datasheets

Primary semiconductor vendor datasheets, errata, and application notes.

DATASHEETonsemi

2N7000, 2N7002, NDS7002A N-Channel Enhancement Mode Field Effect Transistor

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