Power MOSFETsActive

IRLZ44NPbF

Manufacturer: Infineon Technologies

Figures from the datasheet: Infineon Technologies, rev. Rev. 2.1, August 12, 2026

Infineon IRLZ44NPbF N-channel logic-level power MOSFET in TO-220AB, with G-D-S pinout and a drain-connected tab; on-resistance is specified under separate 4 V, 5 V and 10 V gate-drive test conditions.

PackagesTO-220AB
Official Datasheet (PDF)

Technical Overview

01

Technical Overview

The Infineon IRLZ44NPbF is an N-channel logic-level HEXFET power MOSFET documented in datasheet Rev. 2.1, 2026-08-12. Its through-hole TO-220AB package (PG-TO220-3-U05) has gate, drain and source on pins 1, 2 and 3, with the mounting tab connected to drain. The drain-source breakdown voltage V(BR)DSS is specified as at least 55 V at VGS = 0 V, ID = 250 µA and TJ = 25°C. Absolute continuous-drain ratings are 47 A at TC = 25°C and 33 A at TC = 100°C, both at VGS = 10 V; the 110 W absolute power-dissipation rating also requires TC = 25°C. These case-temperature stress ratings are not ambient-temperature, board-current or GPIO-driven load guarantees. The absolute junction-temperature range TJ = −55 to +175°C is distinct from ambient temperature; the listed thermal resistances of 1.4°C/W junction-to-case and 62°C/W junction-to-ambient are maxima. Gate threshold VGS(th) = 1.0–2.0 V is tested at ID = 250 µA and VDS = VGS (TJ = 25°C); it does not establish useful load-current conduction or a digital-input switching threshold. Separately, maximum RDS(on) is 22 mΩ at VGS = 10 V and ID = 25 A, 25 mΩ at VGS = 5 V and ID = 25 A, and 35 mΩ at VGS = 4 V and ID = 21 A, all at TJ = 25°C with pulse width ≤300 µs and duty cycle ≤2%. Use the conditioned tables and the actual thermal and gate-drive design when evaluating a switching application.

Package Pinout & Alternate Functions

Interactive package pinout and pin mapping for TO-220AB-3.

Interactive pinout diagramFront

IRLZ44NPbF: TO-220AB package illustrationInteractive package pinout and pin mapping for TO-220AB.1: G2: D3: S

Package illustration, not a dimensioned mechanical drawing.

3 / 3 pins
#Pin nameType5V TolerantAlternate functions / details
Gpassive—
Gate terminal; voltages are referenced to source. VGS(th) = 1.0–2.0 V at ID = 250 µA, VDS = VGS and TJ = 25°C is a threshold test, not a useful-load drive guarantee or digital logic threshold. Absolute VGS limit: ±16 V.
Dpassive—
Drain terminal (internally connected to the TO-220 mounting tab)
Spassive—
Source terminal and reference for VGS; connected to circuit ground only in an appropriate low-side switching topology, not inherently a ground pin.

Key Specifications

Parametric attributes

ParameterMinTypicalMaxUnitTest condition
Drain-to-Source Breakdown Voltage(V(BR)DSS)55——VVGS = 0 V, ID = 250 µA, TJ = 25°C
Continuous Drain Current at 25°C(ID_25C)——47AAbsolute maximum continuous-drain rating, VGS = 10 V, TC = 25°C (p. 1); case temperature, not ambient temperature or board-current capability.
Continuous Drain Current at 100°C(ID_100C)——33AAbsolute maximum continuous-drain rating, VGS = 10 V, TC = 100°C (p. 1); case temperature, not ambient temperature or board-current capability.
Pulsed Drain Current(IDM)——160AAbsolute maximum repetitive pulsed-drain rating; pulse width limited by maximum junction temperature (note 1, p. 2; see Figure 11). Not a continuous-current allowance.
Static Drain-to-Source On-Resistance at 10V(RDS_ON_10V)——0.022ΩVGS = 10 V, ID = 25 A, TJ = 25°C (Pulse Test: tp <= 300 µs, duty <= 2%)
Static Drain-to-Source On-Resistance at 5V(RDS_ON_5V)——0.025ΩVGS = 5.0 V, ID = 25 A, TJ = 25°C (Pulse Test: tp <= 300 µs, duty <= 2%)
Static Drain-to-Source On-Resistance at 4V(RDS_ON_4V)——0.035ΩVGS = 4.0 V, ID = 21 A, TJ = 25°C (Pulse Test: tp <= 300 µs, duty <= 2%)
Gate Threshold Voltage(VGS_TH)1—2VVDS = VGS, ID = 250 µA, TJ = 25°C
Forward Transconductance(gfs)21——SVDS = 25 V, ID = 25 A, TJ = 25°C (Pulse Test: tp <= 300 µs, duty <= 2%)
Total Gate Charge(Qg)——48nCID = 25 A, VDS = 44 V, VGS = 5.0 V, TJ = 25°C; pulse width ≤300 µs, duty cycle ≤2% (note 4, p. 2; Figures 6 and 13).
Gate-to-Source Charge(Qgs)——8.6nCID = 25 A, VDS = 44 V, VGS = 5.0 V, TJ = 25°C; pulse width ≤300 µs, duty cycle ≤2% (note 4, p. 2; Figures 6 and 13).
Gate-to-Drain Miller Charge(Qgd)——25nCID = 25 A, VDS = 44 V, VGS = 5.0 V, TJ = 25°C; pulse width ≤300 µs, duty cycle ≤2% (note 4, p. 2; Figures 6 and 13).
Input Capacitance(Ciss)—1700—pFVGS = 0 V, VDS = 25 V, f = 1.0 MHz, TJ = 25°C
Output Capacitance(Coss)—400—pFVGS = 0 V, VDS = 25 V, f = 1.0 MHz, TJ = 25°C
Reverse Transfer Capacitance(Crss)—150—pFVGS = 0 V, VDS = 25 V, f = 1.0 MHz, TJ = 25°C
Power Dissipation Absolute Maximum(PD)——110WTC = 25°C, absolute maximum rating (p. 1); case temperature, not ambient temperature. Linear derating factor: 0.71 W/°C.
Junction Temperature Range(TJ)-55—175°COperating junction temperature, absolute maximum ratings (p. 1); not an ambient operating-temperature range.

Absolute Maximum Ratings

Storage temperature-55 – 175 °C
Thermal resistance θJA (TO-220AB)62 °C/W
Thermal resistance θJC (TO-220AB)1.4 °C/W

Hardware Engineering Gotchas

Real-world hardware caveats, PCB layout constraints and silicon errata to know before manufacturing.

Critical

Gate-to-Source Absolute Voltage Limit: ±16 V

The IRLZ44NPbF absolute gate-to-source voltage rating is VGS = ±16 V (p. 1). This is a stress limit, not a guaranteed physical gate-breakdown threshold. Switching transients, coupling through gate-drain capacitance and ringing can change VGS relative to the source node; evaluate both positive and negative excursions in the actual circuit. Exceeding the absolute rating can damage the device.

Mitigation

Evaluate gate-drive voltage and transient protection relative to the source node, including both polarities and clamp tolerance, so actual VGS remains within the absolute rating. If a gate-source clamp is used, check its voltage, pulse capability and effect on normal gate drive; place the protection and gate-return path close to the device. Do not assume a noisy supply rail is an appropriate gate-driver output.

Critical

Gate Charge & Switching Considerations Under Microcontroller Drive

The maximum RDS(on) values are 22 mΩ at VGS = 10 V / ID = 25 A, 25 mΩ at VGS = 5 V / ID = 25 A and 35 mΩ at VGS = 4 V / ID = 21 A, all at TJ = 25°C with pulse width ≤300 µs and duty cycle ≤2% (p. 2, note 4). These are conditioned tests, not a promise of full conduction for every load or thermal state. The datasheet does not specify an RDS(on) limit at 3.3 V gate drive. Total gate charge Qg is at most 48 nC at ID = 25 A, VDS = 44 V, VGS = 5 V and TJ = 25°C, with the same note 4 pulse conditions. Ciss = 1700 pF is a typical value at VGS = 0 V, VDS = 25 V, f = 1 MHz and TJ = 25°C, not a fixed or maximum input capacitance. Actual driver source/sink capability and output impedance affect gate transition times and switching losses; no universal GPIO current capability follows from this MOSFET datasheet.

Mitigation

Evaluate the actual driver output voltage relative to source, its charging and discharging capability, switching frequency and thermal conditions against the applicable resistance and charge tests. Reaching 4 V or 5 V alone does not guarantee a particular load current or acceptable losses. Where required, evaluate a gate driver or buffer capable of the necessary peak source and sink currents, and verify transition times and switching dissipation in the resulting circuit.

Warning

Mounting Tab Electrically Connected to Drain Node

In the TO-220AB package, the metal mounting tab is internally connected to Pin 2 (Drain). In a low-side switching circuit, the drain terminal swings between ground and the load supply voltage. Mounting the tab directly to a grounded heatsink or chassis without electrical insulation bypasses the MOSFET, connecting the load return directly to ground and causing unintended load activation.

Mitigation

When mounting the transistor to a grounded metal enclosure or shared heatsink, always use a thermally conductive electrical insulator pad along with an insulating shoulder washer (bushing) to isolate the mounting screw from the metal tab.

Reference Circuits

IRLZ44N Logic-Level N-Channel MOSFET Low-Side DC Switch

Topology: Low-side N-channel logic-level power switch with gate series damping, 10 kΩ pull-down resistor, inductive flyback clamp diode, and decoupled 12V/24V power rail for MCU control.

Inspect schematicOpen in Web CAD Editor

Official Documentation & Cited Datasheets

Primary semiconductor vendor datasheets, errata, and application notes.

DATASHEETInfineon Technologies

IRLZ44NPbF HEXFET Power MOSFET Datasheet

Help keep this page accurate

Found a pin, package or parameter that does not match the datasheet? Report it.

Report a problem

Opens a public form on GitHub with this page already filled in; a free GitHub account is needed. How reports and confirmations work

Related components

onsemi

2N7000

onsemi 2N7000 N-channel MOSFET in TO-92 (CASE 135AN), S-G-D pinout; absolute VDSS limit 60 V and continuous ID limit 200 mA at TC = 25°C.

onsemi

BSS138

onsemi BSS138 N-channel logic-level MOSFET in SOT-23 (CASE 318-08), G-S-D pinout; absolute VDSS limit 50 V and continuous ID limit 220 mA at TA = 25°C.

Vishay

1N4007

Vishay 1N4007 DO-41 rectifier with VRRM 1000 V maximum and IF(AV) 1 A at TA = 75°C, 9.5 mm leads and a 60 Hz resistive or inductive load.

Vishay

1N4148

Vishay 1N4148 axial DO-35 switching diode. Black cathode band, 75 V continuous reverse-voltage limit and 4 ns maximum reverse recovery under the specified test conditions.