Timing & Oscillators

NE555 Monostable Delay Timer (One-Shot)

The one-shot circuit from the TI NE555 datasheet: press START and the output stays high for a fixed time set by one resistor and one capacitor, about 1.1 s with 100 kΩ and 10 µF.

Operating Supply Voltage
4.5 V – 16 V (TI §7.3)
Components
7
Formulas
2
Gotchas
4
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Schematic workbench

NE555 Monostable Delay TimerExported from CircuitBaseC3100nFR210kΩSW1STARTR1100kΩ+C110µFC210nFTRIG2THRES6CONT5OUT3DISCH7VCC8RESET4GND1U1NE555PVCCGNDGNDGNDGNDGNDOUT

Circuit overview

Operating Supply Voltage
4.5 V – 16 V (TI §7.3)
Components
7
Formulas
2
Gotchas
4

Click any component in the schematic above to inspect its electrical ratings, function, and connections.

Circuit overview

This is Figure 6-2 of the Texas Instruments 555 timer datasheet (SLFS022K), the monostable or one-shot mode. A short low pulse on the trigger input starts a single output pulse whose length depends only on R1 and C1: tw = 1.1 × RA × C. Because the trigger and threshold levels are both fixed fractions of the supply, the pulse length does not change with the supply voltage as long as the supply stays constant during the pulse. TI draws a bare input line; here a START button with a 10 kΩ pull-up drives it, and the values RA = 100 kΩ and C = 10 µF give a pulse of about 1.1 s. A 10 nF capacitor on CONT and a 100 nF supply bypass complete the circuit, the latter as TI recommends in its power-supply section.

Key Technical Specifications

Operating Supply Voltage4.5 V – 16 V (TI §7.3)
Pulse Lengthtw = 1.1 × RA × C ≈ 1.1 s with 100 kΩ and 10 µF (calculated)
Trigger Level1/3 VCC; 1.67 V typical at VCC = 5 V (TI §5.5)
Threshold Level2/3 VCC; 3.3 V typical at VCC = 5 V (TI §5.5)
Supply Sensitivity of Timing0.1 %/V typical, 0.5 %/V maximum, monostable (TI §5.6)
Temperature Coefficient of Timing50 ppm/°C typical, monostable (TI §5.6)
Output Current±200 mA recommended (TI §5.3)

Theory of Operation & Working Principle

01

Waiting state

Between pulses OUT (pin 3) is low and the discharge transistor on DISCH (pin 7) is on, holding C1 near 0 V. R2 keeps TRIG (pin 2) at VCC. RESET (pin 4) is tied to VCC, because a low RESET overrides everything else.

02

Trigger

Pressing START pulls TRIG below the trigger level, one third of VCC (1.67 V typical at VCC = 5 V). The internal flip-flop sets: OUT goes high and the discharge transistor turns off, so C1 is free to charge.

03

Timing

C1 charges through R1 toward VCC:

FORMULA & CALCULATION
VC(t) = VCC(1 - e^(-t/(RA C)))

The pulse ends when V_C reaches the threshold of two thirds of VCC, which happens after ln 3 ≈ 1.1 time constants:

FORMULA & CALCULATION
tw = RA C ln 3 ≈ 1.1 × RA C = 1.1 × 100 kΩ × 10\,µF = 1.1 s

Both levels scale with VCC, so the pulse length does not depend on the supply voltage while it stays constant. TI gives a supply sensitivity of 0.1 %/V typical for this mode.

04

End of the pulse

At the threshold the flip-flop resets: OUT goes low and the discharge transistor turns on and empties C1, ready for the next trigger. TI notes that the sequence ends only if TRIG has been high for at least 10 µs before the end of the interval; if START is still held, OUT stays high until it is released.

05

Output

OUT can source or sink up to 200 mA, enough for an LED with a series resistor, a small relay through a flyback diode, or a logic input.

Design Equations & Calculations

Pulse Length

tw = 1.1 · RA · C

Duration of the output pulse (TI §6.3.1).

SymbolParameterTypical value
RATiming resistor100kΩ
CTiming capacitor10µF
twPulse length (calculated)1.1s

Capacitor Voltage During the Pulse

VC(t) = VCC(1 − e − t/(RA C))

C1 charges toward VCC; the pulse ends when V_C reaches 2/3 VCC, at t = ln 3 · RA·C.

SymbolParameterTypical value
VCCSupply voltage5V
RA CTime constant1s

Bill of Materials (BOM)

Every part needed to build this circuit. Select a reference designator to inspect it on the schematic.

RefDesComponentValue / ratingPackageRole in circuitReference
Precision Timer

TI NE555P; other 555 variants need their own supply and output checks.

NE555PPDIP-8Monostable timerPrecision Timer pinout & datasheet
Resistor100kΩAxial 1/4 WTiming resistor RA—
Aluminium Electrolytic Capacitor

Low-leakage type; + to THRES/DISCH; voltage rating above VCC.

10µFRadialTiming capacitor—
Ceramic Capacitor10nF0805 / radialCONT bypass—
Ceramic Capacitor

Close to pins 8 and 1.

100nF0805 / radialSupply bypass—
Resistor10kΩAxial 1/4 WTrigger pull-up—
Tactile SwitchSTARTSMD / THTTrigger—

Practical Applications & Target Domains

Delay-off timers for lights and fans
Debouncing a switch into one clean pulse
Missing-pulse and timeout detection
Fixed-length pulses for relays, buzzers and logic

Critical Design Traps & Engineering Gotchas

Traps found in real builds, with the fix for each.

Warning

Holding the Button Stretches the Pulse

The pulse ends only if TRIG has been high for at least 10 µs before the timing interval runs out. If START is held longer than tw, OUT stays high until it is released.

Mitigation

Keep the trigger shorter than the pulse. Where the input can stay low, couple it through a small capacitor so that only its falling edge reaches TRIG.

Warning

Electrolytic Leakage with a Large RA

Near the threshold only (VCC − 2/3 VCC)/RA flows into C1, about 17 µA with 100 kΩ at 5 V (calculated). An electrolytic with high leakage takes a noticeable part of that current, lengthens the pulse, and with a very large RA may never reach the threshold.

Mitigation

Keep RA within the 2 kΩ – 100 kΩ range TI uses for its timing specifications and make the time longer with C, using a low-leakage capacitor; use film capacitors for short, accurate pulses.

Note

Floating CONT Pin

CONT carries the internal threshold. Left open, noise coupled into it moves the threshold and makes the pulse length jitter.

Mitigation

Bypass CONT to ground with a small capacitor (10 nF here), as TI draws in Figure 6-2.

Note

RESET Left Unconnected

RESET is active low and overrides the trigger. Left floating it can pick up noise and end or block pulses.

Mitigation

Tie RESET to VCC as drawn, or drive it from logic if the pulse must be cancelled.

Primary sources

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