LM393 Precision Voltage Comparator with Hysteresis

The circuit operates from a single +5.0 V DC power rail connected to Pin 8 (VCC) and Pin 4 (GND). Supply bypass capacitor C1 (100 nF X7R ceramic) provides a localized low-impedance charge reservoir directly across the IC power pins, absorbing high-frequency transient current spikes generated when the open-collector output stage switches rapidly between cutoff and deep saturation. The LM393 input architecture uses PNP differential Darlington pairs with integrated level shifting, allowing both input terminals to sense voltages down to true circuit ground (0 V) without requiring a negative supply rail.

A stable reference voltage V_REF is derived from the +5.0 V supply rail using a matched voltage divider formed by R1 (10 kΩ) and R2 (10 kΩ). With 1% tolerance metal film resistors, the midpoint reference voltage presented to Pin 2 (Inverting Input, 1IN-) is:

This 2.50 V threshold is centered within the device linear common-mode input range (0 V to VCC - 1.5V = 3.5V), providing optimal differential headroom for both positive and negative signal swings.

The analog input signal VIN enters via series resistor R3 (10 kΩ) and terminates at summing node junction j_in_pos before entering Pin 3 (Non-Inverting Input, 1IN+). Positive feedback resistor R4 (1 MΩ) couples the comparator output state back to this summing junction. Applying superposition, the instantaneous voltage V+ at Pin 3 is governed by both VIN and the comparator output voltage VOUT:

Because R4 is one hundred times larger than R3 (R4 / R3 = 100), the feedback network injects a small, controlled 1% fraction of the output swing into the non-inverting node, dynamically shifting the effective switching threshold depending on the current output state.

When VIN is low, the comparator output is held high (VOH ≈ 5.0 V via pull-up resistor R5). The current flowing through R4 raises the potential at Pin 3, establishing the Upper Trip Point (VTH ≈ 2.524 V). When VIN rises above VTH, the internal differential amplifier flips state, turning ON the internal open-collector NPN transistor and pulling VOUT down to saturation (VOL ≈ 0.1 V). Instantly, R4 shifts the Pin 3 threshold down to the Lower Trip Point (VTL ≈ 2.475 V). The difference between these thresholds defines the hysteresis window:

This 48.5 mV noise margin prevents false triggering, parasitic bursts, and output chattering when evaluating slow-ramping sensor inputs or noisy analog signals.

The LM393 output stage consists of an uncommitted bipolar NPN transistor with an open collector connected directly to Pin 1. Pull-up resistor R5 (4.7 kΩ) tied to +5.0 V restores active high logic levels (VOH = 5.0 V) when the output transistor is in cutoff. When the comparator triggers LOW, the internal switch sinks ISINK = (5.0V - 0.15V) / 4.7kΩ ≈ 1.03 mA, driving the output cleanly to VOL ≤ 150 mV. Because the pull-up rail is electrically isolated from the comparator core, R5 can alternatively be tied to an external +3.3 V microcontroller rail, achieving seamless direct logic level translation without active level-shifter ICs.