Timers & Gate DriversActive

ULN2003A

Manufacturer: Texas Instruments

Figures from the datasheet: Texas Instruments SLRS027P, rev. Rev. P, February 2017

Texas Instruments ULN2003A 7-channel Darlington transistor array in PDIP-16 and SOIC-16; 50 V collector breakdown, 500 mA continuous sink current per channel, and integrated inductive transient suppression clamp diodes.

PackagesPDIP-16, SOIC-16
Supply voltage0 – 50 V
Temperature range-20 – 70 °C

Technical Overview

01

Technical Overview

The ULN2003A is an industry-standard monolithic high-voltage, high-current Darlington transistor array manufactured by Texas Instruments (datasheet SLRS027P, revised February 2017). Comprising seven independent NPN Darlington pairs sharing a common emitter ground connection (Pin 8), the ULN2003A provides robust low-side sinking capability up to 500 mA continuous (600 mA peak) per channel with an off-state collector breakdown voltage rating of 50 V. Each channel incorporates an integrated 2.7 kΩ series base resistor coupled with internal base-emitter pulldown resistors, enabling direct logic interfacing to 5 V TTL, CMOS, and microcontrollers without external current-limiting passives. The device features integrated transient suppression clamp diodes sharing a common cathode terminal (Pin 9, COM); connecting Pin 9 to the positive load supply rail protects the open-collector output stages against destructive high-voltage inductive kickback spikes generated when de-energizing relays, solenoids, stepper motor coils, and inductive actuators. Outputs may be paralleled to deliver higher aggregate load currents. Standard packages include 16-pin plastic dual-in-line (PDIP-16, N package) and 16-pin small-outline integrated circuit (SOIC-16, D package), with total package power dissipation governed by thermal resistances of 67°C/W and 73°C/W respectively.

Package Pinout & Alternate Functions

Interactive package pinout and pin mapping for PDIP-16.

Interactive pinout diagramTop

ULN2003A: PDIP-16 package illustrationInteractive package pinout and pin mapping for PDIP-16.1: 1B2: 2B3: 3B4: 4B5: 5B6: 6B7: 7B8: E16: 1C15: 2C14: 3C13: 4C12: 5C11: 6C10: 7C9: COM

Package illustration, not a dimensioned mechanical drawing.

16 / 16 pins
#Pin nameType5V TolerantAlternate functions / details
1Binput onlyYes
Darlington pair 1 base input (active-high 5V TTL/CMOS logic input with integrated 2.7 kΩ series base resistor)
2Binput onlyYes
Darlington pair 2 base input (active-high 5V TTL/CMOS logic input with integrated 2.7 kΩ series base resistor)
3Binput onlyYes
Darlington pair 3 base input (active-high 5V TTL/CMOS logic input with integrated 2.7 kΩ series base resistor)
4Binput onlyYes
Darlington pair 4 base input (active-high 5V TTL/CMOS logic input with integrated 2.7 kΩ series base resistor)
5Binput onlyYes
Darlington pair 5 base input (active-high 5V TTL/CMOS logic input with integrated 2.7 kΩ series base resistor)
6Binput onlyYes
Darlington pair 6 base input (active-high 5V TTL/CMOS logic input with integrated 2.7 kΩ series base resistor)
7Binput onlyYes
Darlington pair 7 base input (active-high 5V TTL/CMOS logic input with integrated 2.7 kΩ series base resistor)
Eground—
Common emitter ground terminal for all 7 Darlington driver channels (max 2.5 A continuous return current)
COMpower in—
Common cathode terminal for integrated flyback suppression clamp diodes (must connect to load positive power supply rail when driving inductive loads)
7Copen drainNo
Darlington pair 7 open-collector output (sinks up to 500 mA continuous / 600 mA peak to ground; protected by clamp diode to COM)
6Copen drainNo
Darlington pair 6 open-collector output (sinks up to 500 mA continuous / 600 mA peak to ground; protected by clamp diode to COM)
5Copen drainNo
Darlington pair 5 open-collector output (sinks up to 500 mA continuous / 600 mA peak to ground; protected by clamp diode to COM)
4Copen drainNo
Darlington pair 4 open-collector output (sinks up to 500 mA continuous / 600 mA peak to ground; protected by clamp diode to COM)
3Copen drainNo
Darlington pair 3 open-collector output (sinks up to 500 mA continuous / 600 mA peak to ground; protected by clamp diode to COM)
2Copen drainNo
Darlington pair 2 open-collector output (sinks up to 500 mA continuous / 600 mA peak to ground; protected by clamp diode to COM)
1Copen drainNo
Darlington pair 1 open-collector output (sinks up to 500 mA continuous / 600 mA peak to ground; protected by clamp diode to COM)

Key Specifications

Parametric attributes

ParameterMinTypicalMaxUnitTest condition
Collector-Emitter Saturation Voltage (100 mA)(VCE(sat)_100)—0.91.1VIC = 100 mA, IB = 250 µA, TA = 25°C
Collector-Emitter Saturation Voltage (200 mA)(VCE(sat)_200)—1.11.3VIC = 200 mA, IB = 350 µA, TA = 25°C
Collector-Emitter Saturation Voltage (350 mA)(VCE(sat)_350)—1.31.6VIC = 350 mA, IB = 500 µA, TA = 25°C
Collector Cutoff Current(ICEX)—0.150µAVCE = 50 V, IB = 0, TA = 25°C
On-State Input Current(II(on))—0.931.35mAVI = 3.85 V, TA = 25°C
On-State Input Voltage (200 mA)(VI(on)_200)—2.12.4VVCE = 2 V, IC = 200 mA, TA = 25°C
On-State Input Voltage (300 mA)(VI(on)_300)—2.43VVCE = 2 V, IC = 300 mA, TA = 25°C
Clamp Diode Forward Voltage(VF)—1.72VIF = 350 mA, TA = 25°C
Clamp Diode Reverse Current(IR)—0.150µAVR = 50 V, TA = 25°C
DC Current Transfer Ratio(hFE)10001000——VCE = 2 V, IC = 150 mA, TA = 25°C
Turn-On Propagation Delay(tPLH)—0.251µsVI = 3 V to 50% output low, RL = 100 Ω
Turn-Off Propagation Delay(tPHL)—0.251µsVI = 3 V to 50% output high, RL = 100 Ω
Input Capacitance(CI)—15—pFVI = 0, f = 1 MHz, TA = 25°C
Continuous Collector Current per Channel(IC_cont)—500500mASingle channel conducting, TA = 25°C
Total Ground Return Current(IE_total)—15002500mACommon emitter Pin 8 return current

Absolute Maximum Ratings

Max supply voltage (VDD/VCC)50 V
Max input voltage30 V
Max output / pin current500 mA
Junction temperature-20 – 70 °C
Storage temperature-65 – 150 °C
Thermal resistance θJA (PDIP-16)67 °C/W
Thermal resistance θJA (SOIC-16)73 °C/W

Hardware Engineering Gotchas

Real-world hardware caveats, PCB layout constraints and silicon errata to know before manufacturing.

Critical

Unconnected COM Clamp Pin (Pin 9) on Inductive Loads Causing Collector Breakdown

Each driver channel incorporates an internal fast freewheeling clamp diode whose cathode connects to Pin 9 (COM) and anode to the channel collector. When switching inductive loads (relays, solenoids, stepper motor phases), collapsing magnetic fields induce high-voltage kickback transients (V = -L * di/dt). If Pin 9 is left floating or tied to an incorrect rail, these inductive spikes exceed the 50V collector-emitter breakdown rating, causing destructive avalanche breakdown of the Darlington output transistors and permanent channel failure.

Mitigation

Always connect Pin 9 (COM) directly to the positive power supply rail that feeds the inductive loads (e.g. +5V, +12V, or +24V). If driving purely resistive loads such as LEDs, Pin 9 may be left floating, though tying it to the positive rail provides added noise immunity.

Critical

Total Package Power Dissipation and Ground Lead Current Constraints

While each individual channel is rated for up to 500 mA continuous collector sink current, all 7 channels conducting simultaneously at 500 mA would require 3.5 A total return current through the single ground lead (Pin 8), exceeding the absolute maximum ground pin rating of 2.5 A. Furthermore, at high continuous current, the cumulative saturation voltage drop across all active channels dissipates significant power, quickly exceeding the package thermal rating (1.15 W at 25°C ambient, RthetaJA = 67°C/W for PDIP-16, 73°C/W for SOIC-16) and causing thermal runaway.

Mitigation

Calculate total package dissipation: P_total = sum(V_CE(sat) * I_C * DutyCycle) + sum(V_I * I_I). When driving all 7 channels continuously at 100% duty cycle, derate individual channel currents to <= 150 mA to 200 mA. For heavy loads, multiplex channels, parallel adjacent outputs, or upgrade to a DMOS sink driver such as the Toshiba TBD62003A.

Warning

Darlington Output Saturation Voltage Drop (0.9V to 1.6V) and Load Voltage Penalty

Because a Darlington pair consists of two cascaded NPN bipolar transistors where the output stage cannot saturate below V_BE2 + V_CE(sat)1, the on-state saturation voltage drop V_CE(sat) is significantly higher than a single saturated BJT or low-RDS(on) MOSFET. At 100 mA, V_CE(sat) is typically 0.9 V to 1.1 V; at 350 mA, it climbs to 1.3 V to 1.6 V. When driving low-voltage loads (such as a 5V relay coil or 3.3V indicators), this 1V+ loss deprives the load of required terminal voltage (a 5V coil receives only 3.7V to 4.1V) while dissipating continuous heat inside the IC.

Mitigation

Verify that inductive coils reliably pull in at reduced terminal voltage (V_LOAD = V_SUPPLY - V_CE(sat)). For 5V relays, verify that coil pick-up voltage is <= 3.75V (75% of nominal). In battery-powered or 3.3V systems where a 1V drop is intolerable, replace the bipolar ULN2003A with a DMOS driver array (such as TBD62003A) exhibiting sub-ohm on-resistance.

Warning

3.3V Microcontroller Logic Drive Limitations (Insufficient Base Overdrive)

The ULN2003A internal 2.7 kΩ series base resistor is sized specifically for 5V TTL and CMOS logic levels. When driven from a modern 3.3V microcontroller (such as ESP32, RP2040, or STM32), the available base voltage across the two Darlington base-emitter junctions (2 * V_BE approx 1.4V to 1.7V) yields only (3.3V - 1.5V) / 2.7k = 0.67 mA of base drive. While sufficient to sink light currents up to 100 mA, this reduced base current cannot drive the output stage into full saturation at heavier collector currents (300 mA to 500 mA), resulting in elevated V_CE, increased power dissipation, and excessive package heating.

Mitigation

For 3.3V logic systems switching heavy loads (> 150 mA per channel), use the low-voltage optimized ULN2003LV (specifically designed for 1.8V to 5V inputs) or Toshiba TBD62003A (DMOS inputs with low threshold), or buffer the 3.3V GPIOs using a 5V level shifter such as the 74HCT245 or discrete BSS138 circuit.

Cross-Reference & Equivalents

Part number (MPN)ManufacturerCompatibilityElectrical differences / BOM considerations
ULN2003ANTexas Instrumentspin to pin drop inExact manufacturer orderable part number for ULN2003A in standard 16-pin PDIP (N package) through-hole outline.
ULN2003ADRTexas Instrumentspin to pin drop inExact manufacturer orderable part number for ULN2003A in 16-pin SOIC (D package) surface-mount outline on tape and reel.
MC1413PON Semiconductorpin to pin drop inDirect second-source pin-compatible 7-channel Darlington driver array in PDIP-16 with identical 50 V / 500 mA electrical ratings.
TBD62003APGToshibadiffering electrical limitsModern BiCD DMOS 7-channel sink driver in pin-compatible DIP-16; replaces bipolar Darlington pairs with low RDS(on) DMOS transistors, virtually eliminating VCE(sat) voltage drop and heat dissipation.

Reference Circuits

ULN2003A 7-Channel Relay & Solenoid Inductive Load Driver

Topology: Seven-channel Darlington open-collector sink driver with integrated common-cathode freewheeling clamp diodes and power-rail decoupling for 12V relays, solenoids, and stepper coils.

Official Documentation & Cited Datasheets

Primary semiconductor vendor datasheets, errata, and application notes.

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