Logic ICs & Shift RegistersActive

SN74AUC1G14DBVR

Manufacturer: Texas Instruments

Figures from the datasheet: Texas Instruments, rev. SCES375P, June 2017

Single inverting Schmitt-trigger gate in Texas Instruments Advanced Ultra-Low-Voltage CMOS (AUC) technology, operating from 0.8 V to 2.7 V with 3.6 V tolerant inputs and partial-power-down Ioff support.

PackagesSOT-23-5, SC-70-5
Supply voltage0.8 – 2.7 V
Temperature range-40 – 85 °C
Official Datasheet (PDF)

Technical Overview

01

Technical Overview

The SN74AUC1G14 is a single inverter gate with Schmitt-trigger inputs from Texas Instruments' Advanced Ultra-Low-Voltage CMOS (AUC) logic family, performing the Boolean function Y = \bar{A}. Optimized for 1.65 V to 1.95 V VCC operation, the device is operational across a recommended supply range of 0.8 V to 2.7 V. The Schmitt-trigger input provides distinct positive-going (VT+) and negative-going (VT-) threshold voltages with defined input hysteresis (\Delta VT), converting slow or noisy input transitions into well-defined digital transitions without output chatter.

Fabricated in sub-micron CMOS, the device delivers high-speed propagation delays (typical tpd of 1.2 ns at 1.8 V, CL = 15 pF) with characterized drive levels up to |IOH| = 8 mA and IOL = 8 mA at VCC = 1.65 V. While input terminals are 3.6 V tolerant across the entire recommended operating range (enabling down-translation from 2.5 V or 3.3 V systems to lower-voltage domains), output voltage limits depend strictly on operating state: recommended output voltage in the active state is restricted to 0 V to VCC (absolute maximum -0.5 V to VCC + 0.5 V), whereas 3.6 V output tolerance applies only in the high-impedance or power-off state (VCC = 0 V). The device includes partial-power-down circuitry (Ioff): with VCC = 0 V, input and output leakage is restricted to at most ±10 µA at the 2.7 V test point, preventing backflow into unpowered rails. Exceeding absolute maximum ratings (3.6 V on VCC and inputs) may cause permanent device damage.

Package Pinout & Alternate Functions

Interactive package pinout and pin mapping for SOT-23-5.

Interactive pinout diagramTop

SN74AUC1G14DBVR: SOT-23-5 package illustrationInteractive package pinout and pin mapping for SOT-23-5.1: NC2: A3: GND5: VCC4: Y

Package illustration, not a dimensioned mechanical drawing.

5 / 5 pins
#Pin nameType5V TolerantAlternate functions / details
NCpassive—
No internal connection (leave floating or tie to GND or VCC)
Ainput onlyNo
Schmitt-trigger logic data input (3.6 V tolerant, no internal pull-up or pull-down resistors)
GNDground—
Ground reference terminal (0 V)
Ypower out—
Inverted push-pull logic output (Y = NOT A, supports partial-power-down Ioff isolation)
VCCpower in—
Positive power supply terminal (0.8 V to 2.7 V recommended, 3.6 V absolute maximum)

Key Specifications

Parametric attributes

ParameterMinTypicalMaxUnitTest condition
Operating Supply Voltage Range(VCC)0.81.82.7VTA = -40°C to 85°C (optimized for 1.65 V to 1.95 V)
Positive-Going Input Threshold Voltage (1.65V)(VT+)0.79—1.16VVCC = 1.65 V, IO = 0, TA = -40°C to 85°C
Negative-Going Input Threshold Voltage (1.65V)(VT-)0.39—0.62VVCC = 1.65 V, IO = 0, TA = -40°C to 85°C
Input Hysteresis Voltage (1.65V)(Delta VT)0.37—0.62VVCC = 1.65 V, IO = 0
Positive-Going Input Threshold Voltage (0.8V)(VT+(0.8V))—0.5—VVCC = 0.8 V, IO = 0, TA = 25°C
Negative-Going Input Threshold Voltage (0.8V)(VT-(0.8V))—0.3—VVCC = 0.8 V, IO = 0, TA = 25°C
Input Hysteresis Voltage (0.8V)(Delta VT(0.8V))—0.21—VVCC = 0.8 V, IO = 0, TA = 25°C
High-Level Output Current Magnitude (1.65V)(|IOH|)——8mAVCC = 1.65 V, VOH >= 1.2 V, TA = -40°C to 85°C (TI convention: IOH = -8 mA sourcing)
Low-Level Output Current (1.65V)(IOL)——8mAVCC = 1.65 V, VOL <= 0.45 V, TA = -40°C to 85°C
Propagation Delay (1.8V, CL = 15 pF)(tpd)0.51.21.9nsVCC = 1.8 V ± 0.15 V, CL = 15 pF, RL = 2 kΩ, TA = -40°C to 85°C
Partial-Power-Down Leakage Current(Ioff)——10µAVCC = 0 V, VI or VO = 2.7 V, TA = -40°C to 85°C
Quiescent Supply Current(ICC)——10µAVCC = 0.8 V to 2.7 V, VI = VCC or GND, IO = 0, TA = -40°C to 85°C
Input Capacitance(Ci)—3.5—pFVCC = 2.5 V, VI = VCC or GND, TA = 25°C

Absolute Maximum Ratings

Max supply voltage (VDD/VCC)3.6 V
Max input voltage3.6 V
Max output / pin current20 mA
Storage temperature-65 – 150 °C
ESD rating (HBM)2000 V
Thermal resistance θJA (SOT-23-5)206 °C/W
Thermal resistance θJA (SC-70-5)252 °C/W

Hardware Engineering Gotchas

Real-world hardware caveats, PCB layout constraints and silicon errata to know before manufacturing.

Critical

Absolute Maximum Supply and Input Voltage is 3.6 V (Not 5 V Tolerant)

Unlike standard 5V CMOS logic (74HC/HCT) or 5V-tolerant low-voltage logic (74LVC), the AUC family is rated strictly for a maximum recommended VCC of 2.7V and an absolute maximum VCC and input voltage VI of 3.6V. Connecting inputs to 5V logic rails or operating above absolute maximum ratings may cause permanent device damage or compromise long-term reliability.

Mitigation

Ensure supply rails do not exceed 2.7 V (nominal 1.8 V, 1.5 V, or 1.2 V). When interfacing from 5 V systems, use dedicated level translators or potential dividers to keep input voltages within the 3.6 V rating.

Warning

Input Threshold Dependence on Supply Voltage (VCC)

Schmitt-trigger switching thresholds vary with supply voltage VCC and temperature. For example, at VCC = 1.65 V and TA = -40°C to 85°C, VT+ ranges from 0.79 V to 1.16 V, while at VCC = 2.3 V it spans 1.11 V to 1.56 V. Similarly, minimum hysteresis Delta VT is 0.37 V at 1.65 V and 0.48 V at 2.3 V (0.21 V typical at 0.8 V, 25°C). In RC relaxation oscillators or timing-delay circuits, supply fluctuations alter switching points and impact output timing.

Mitigation

Use a well-regulated supply rail for timing-sensitive circuits, and verify threshold boundaries across the expected operating voltage and temperature envelope (-40°C to 85°C).

Warning

Floating Inputs Cause Excessive Supply Current (ICC)

Although the Schmitt-trigger input has hysteresis and tolerates slow transition edges without output oscillation or chatter, holding an input in the indeterminate threshold region causes both internal NMOS and PMOS input transistors to partially conduct, dramatically increasing quiescent supply current beyond the 10µA specification (per TI application report SCBA004).

Mitigation

As specified in Section 6.3 Note 1, all unused inputs must be tied to VCC or GND. In applications with high-impedance tri-state inputs, add external pull-up or pull-down resistors to define the logic level.

Warning

Output Drive Limitations at Low Supply Voltages (VCC < 1.2V)

While the SN74AUC1G14 functions down to 0.8 V, output drive capability decreases significantly at lower supply voltages: specified drive current is ±9 mA at 2.3 V (VOH >= 1.8 V, VOL <= 0.6 V) and ±8 mA at 1.65 V (VOH >= 1.2 V, VOL <= 0.45 V), decreasing to ±3 mA at 1.1 V and ±0.7 mA at 0.8 V. In addition, typical propagation delay tpd increases from 1.2 ns at 1.8 V to 5.8 ns at 0.8 V into a 15 pF load.

Mitigation

Ensure downstream circuit loading conforms to low-voltage drive ratings, and account for increased propagation delays when operating at sub-1.2 V supply rails.

Official Documentation & Cited Datasheets

Primary semiconductor vendor datasheets, errata, and application notes.

DATASHEETTexas Instruments

SN74AUC1G14 Single Schmitt-Trigger Inverter Datasheet

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