L293D Dual H-Bridge DC Motor Driver

Each half-H driver channel inside U1 employs an NPN Darlington pull-up transistor pair and an NPN common-emitter pull-down transistor. When driving a motor terminal HIGH, output current flows from the motor supply VCC2 through the upper Darlington pair into the load. Due to the two series base-emitter and collector-emitter junctions in the Darlington configuration, the high-side saturation voltage drop ranges between 1.2V and 1.8V. Simultaneously, the low-side pull-down transistor sinks the motor current from the opposite terminal to ground, incurring a low-side saturation drop of 1.0V to 1.5V. Consequently, the effective voltage delivered to the motor terminals is reduced by the cumulative two-transistor saturation loss:

Motor 1 is connected differentially between output pins 1Y (Pin 3) and 2Y (Pin 6). Directional rotation is dictated by complementary TTL logic levels on inputs 1A (Pin 2) and 2A (Pin 7) while enable pin 1,2EN (Pin 1) is asserted HIGH: - Forward Rotation: Setting 1A = HIGH and 2A = LOW drives 1Y HIGH (~VCC2 - 1.4V) and 2Y LOW (~1.2V), establishing forward current flow from Pin 3 through Motor 1 to Pin 6. - Reverse Rotation: Setting 1A = LOW and 2A = HIGH drives 1Y LOW and 2Y HIGH, reversing terminal polarity and reversing motor rotation. - Active Dynamic Braking: Setting both inputs to identical logic levels (1A = HIGH, 2A = HIGH or 1A = LOW, 2A = LOW) clamps both motor terminals to the same potential, dissipating motor back-EMF into low-impedance paths and rapidly braking rotor rotation.

Continuous motor torque and rotational velocity regulation is achieved by injecting a pulse-width modulated (PWM) digital waveform into enable pin 1,2EN (for Motor 1) or 3,4EN (for Motor 2) at typical frequencies of 1 kHz to 10 kHz. When the enable pin transitions to logic LOW, both half-H push-pull output stages enter a high-impedance (Hi-Z) tri-state mode, effectively disconnecting the motor from both VCC2 and ground. The motor coasts freely while circulating armature currents decay through internal clamp diodes. The effective average terminal voltage scales proportionally with duty cycle:

Direct-current permanent-magnet motors represent complex inductive loads described by winding inductance L and back-electromotive force constant Ke. When driver transistors switch abruptly from ON to OFF, the collapsing magnetic field inside the motor windings induces an instantaneous inductive flyback spike (\(V = -L \cdot \frac{di}{dt}\)). In the L293D, integrated internal clamping diodes bridge each output channel to both VCC2 and GND: - If an output spikes above VCC2, the high-side diode forward-biases, clamping the terminal to \(V_{CC2} + V_F\) (typically VCC2 + 1.2V). - If an output swings below ground, the low-side diode forward-biases, clamping the terminal to \(-V_F\) (typically -1.2V). This recirculation prevents bipolar collector-base avalanche breakdown. Parallel ceramic capacitors C4 and C5 (100nF) located directly across the motor terminals provide a localized low-impedance bypass for high-frequency brush commutation noise.

To isolate sensitive microcontroller digital logic from violent motor switching transients, U1 features separated power inputs: VCC1 (Pin 16) powers internal TTL input comparators, logic buffers, and thermal sensors, decoupled by ceramic capacitor C1 (100nF). VCC2 (Pin 8) supplies exclusively the high-current output stages, decoupled by parallel bulk electrolytic capacitor C2 (100µF, absorbing surge currents and ripple) and high-frequency ceramic capacitor C3 (100nF, shunting fast dI/dt edge harmonics). Internal cross-conduction interlocking prevents top and bottom transistors in the same half-H column from conducting simultaneously, eliminating catastrophic shoot-through current spikes during logic switching transitions.