Op-Amps & ComparatorsObsolete

LMC6482AIM/NOPB

Manufacturer: Texas Instruments

Figures from the datasheet: Texas Instruments, rev. SNOS674J, September 2024

Dual CMOS rail-to-rail input and output operational amplifier in SOIC-8, with 20 fA typical input bias current and 82 dB typical CMRR under specified conditions; recommended total supply span is 3.0 V to 15.5 V.

PackagesSOIC-8
Supply voltage3 – 15.5 V
Official Datasheet (PDF)

Technical Overview

01

Technical Overview

The TI LMC6482AIM/NOPB is a dual CMOS operational amplifier in SOIC-8. Its recommended total supply span VS = (V+) - (V-) is 3.0 V to 15.5 V. For the 5 V and 15 V common-mode tests with V- = 0 V and CMRR >= 50 dB, the range at 25°C typically extends 0.25 V beyond the rails; specified boundary values extend 0.3 V beyond the rails. Over TA = -40°C to 85°C the specified range is V- to V+. No phase inversion at the rails does not remove the input-voltage and current limits.

Rail-to-rail output swing depends on load, supply and temperature. The datasheet feature summary states within 20 mV of the rails with a light 100 kΩ load. At V+ = 5 V, V- = 0 V and RL = 2 kΩ to 2.5 V, the 25°C output bounds are VOH >= 4.8 V and VOL <= 0.18 V (typical 4.9 V and 0.1 V); full-temperature bounds are 4.7 V and 0.24 V. These are conditioned values, not a guarantee of a zero-volt output under arbitrary sinking current.

Typical GBW is 1.5 MHz at 15 V, typical slew rate is 1.3 V/µs for the specified 15 V, 10 V-step test, and typical phase margin is 50° under the 5 V table conditions. Open-loop comparator performance is not characterized. The device typically drives 100 pF directly at VS = 15 V in unity gain without oscillation; actual capacitive-load stability depends on circuit conditions. Input bias current magnitude is typically 20 fA at 25°C, with a 4.0 pA maximum over TA = -40°C to 85°C under the stated 5 V test conditions. Guarding and clean layout help control surface-leakage errors in high-impedance circuits.

The TI Package Option Addendum dated 5-Mar-2026 lists LMC6482AIM/NOPB as Obsolete. Active LMC6482AIMX/NOPB (SOIC tape-and-reel) and LMC6482AIN/NOPB (PDIP tube) are distinct orderables; their status is not transferred to this selected part.

Package Pinout & Alternate Functions

Interactive package pinout and pin mapping for SOIC-8.

Interactive pinout diagramTop

LMC6482AIM/NOPB: SOIC-8 package illustrationInteractive package pinout and pin mapping for SOIC-8.1: OUT_A2: IN_A_NEG3: IN_A_POS4: V_MINUS8: V_PLUS7: OUT_B6: IN_B_NEG5: IN_B_POS

Package illustration, not a dimensioned mechanical drawing.

8 / 8 pins
#Pin nameType5V TolerantAlternate functions / details
OUT_Aanalog out—
Channel A output terminal (rail-to-rail swing within 20 mV of rails at 100 kΩ load)
IN_A_NEGanalog inNo
Channel A inverting input terminal (-)
IN_A_POSanalog inNo
Channel A non-inverting input terminal (+)
V_MINUSpower in—
Negative power supply terminal (connects to 0 V ground in single-supply or negative rail in split-supply operation)
IN_B_POSanalog inNo
Channel B non-inverting input terminal (+)
IN_B_NEGanalog inNo
Channel B inverting input terminal (-)
OUT_Banalog out—
Channel B output terminal (rail-to-rail swing within 20 mV of rails at 100 kΩ load)
V_PLUSpower in—
Positive power supply terminal (recommended total supply span VS = (V+) - (V-) of 3.0 V to 15.5 V, absolute maximum 16.0 V differential)

Key Specifications

Parametric attributes

ParameterMinTypicalMaxUnitTest condition
Input Offset Voltage Magnitude (A-Grade)(|VOS|)—0.110.75mVVS = 5 V, V- = 0 V, VCM = VO = 2.5 V, RL > 1 MΩ, TJ = 25°C (A-grade)
Input Offset Voltage Average Drift Magnitude(|TCVOS|)—1—µV/°CVS = 5 V, V- = 0 V, VCM = VO = 2.5 V, RL > 1 MΩ, TA = -40°C to 85°C
Input Bias Current Magnitude(|IB|)—0.024pAVS = 5 V, V- = 0 V, VCM = VO = 2.5 V, RL > 1 MΩ; typical at TJ = 25°C, maximum over TA = -40°C to 85°C
Input Offset Current Magnitude(|IOS|)—0.012pAVS = 5 V, V- = 0 V, VCM = VO = 2.5 V, RL > 1 MΩ; typical at TJ = 25°C, maximum over TA = -40°C to 85°C
Common-Mode Rejection Ratio(CMRR)7082—dBV+ = 5 V, V- = 0 V, 0 V <= VCM <= 5 V, VO = 2.5 V, RL > 1 MΩ, TJ = 25°C (A-grade)
Positive Power Supply Rejection Ratio (+PSRR)(+PSRR)7082—dB5 V <= V+ <= 15 V, V- = 0 V, VCM = VO = 2.5 V, RL > 1 MΩ, TJ = 25°C (A-grade)
High-Level Output Voltage Swing(VOH)4.84.9—VV+ = 5 V, V- = 0 V, VCM = 2.5 V, RL = 2 kΩ to 2.5 V, TJ = 25°C
Low-Level Output Voltage Swing(VOL)—0.10.18VV+ = 5 V, V- = 0 V, VCM = 2.5 V, RL = 2 kΩ to 2.5 V, TJ = 25°C
Gain Bandwidth Product(GBW)—1.5—MHzV+ = 15 V, V- = 0 V, VCM = VO = 7.5 V, RL > 1 MΩ, TJ = 25°C
Slew Rate(SR)11.3—V/µsV+ = 15 V, V- = 0 V, 10 V step, RL > 1 MΩ, TJ = 25°C; A-grade, slower of positive and negative slew rates (footnote 2)
Supply Current per Amplifier(IS)—500700µAV+ = 5 V, V- = 0 V, VCM = VO = 2.5 V, RL > 1 MΩ, TJ = 25°C; per amplifier
Input Voltage Noise Density (1 kHz)(en)—37—nV/√HzV+ = 5 V, V- = 0 V, VCM = 1 V, VO = 2.5 V, RL > 1 MΩ, f = 1 kHz, TJ = 25°C
Phase Margin(phi_m)—50—degV+ = 5 V, V- = 0 V, VCM = VO = 2.5 V, RL > 1 MΩ, TJ = 25°C
Recommended Junction Temperature(TJ_rec)-40—85°CSection 5.3 junction-temperature range; not an ambient-temperature rating
Absolute Maximum Junction Temperature(TJ_abs)——150°CSection 5.1 absolute stress limit; functional operation is not implied
Absolute Maximum Output Pin Current Magnitude(|IO_abs|)——30mASection 5.1: ±30 mA absolute stress, not linear drive capability; long-term excess current affects reliability; do not short output to V+ when V+ > 13 V

Absolute Maximum Ratings

Max supply voltage (VDD/VCC)16 V
Storage temperature-65 – 150 °C
ESD rating (HBM)1500 V
Thermal resistance θJA (SOIC-8)128.9 °C/W
Thermal resistance θJC (SOIC-8)68.6 °C/W

Hardware Engineering Gotchas

Real-world hardware caveats, PCB layout constraints and silicon errata to know before manufacturing.

Warning

Output Sinking Voltage Drop Near Negative Rail (GND)

Output swing depends on sourcing or sinking current, supply and temperature. At V+ = 5 V, V- = 0 V and a 2 kΩ load connected to 2.5 V, VOL is typically 0.1 V with a 0.18 V maximum at 25°C; the maximum over TA = -40°C to 85°C is 0.24 V. Rail-to-rail does not mean a zero-volt output at every load.

Mitigation

Determine the required output range and load current, then use the conditioned output-swing specifications to check the circuit error budget. Validate any different supply or external output-bias arrangement against total supply, input/common-mode, current, thermal and stability limits; a rail change alone does not remove offset or other errors.

Warning

Capacitive Load Phase Margin Reduction

Driving external capacitive loads interacts with the op amp open-loop output impedance, introducing an additional pole that reduces phase margin. While the device typically drives up to 100 pF directly at VS = 15 V in unity-gain without oscillation, larger capacitive loads or lower supply voltages can cause gain peaking, ringing, or instability.

Mitigation

TI Figure 7-8 illustrates a 300 Ω series isolation resistor with a 330 pF load outside the feedback loop. Figure 7-10 illustrates a 300 Ω resistor and a 100 pF AC feedback capacitor with a 330 pF load. These are application examples, not universal component values: choose and verify compensation for the actual circuit and desired pulse response.

Warning

PCB Surface Leakage Exceeding Femtoampere Input Bias Current

With a typical input bias current of only 20 fA at 25°C, parasitic PCB surface leakage can easily exceed native bias current by orders of magnitude (for instance, 5 V across 10^12 Ω leakage resistance injects 5 pA, which is 250 times the typical bias current). Solder flux residue, surface ionic contamination, and humidity degrade board insulation.

Mitigation

Surround high-impedance input traces with guard rings on top and bottom PCB layers driven at the same potential as the inputs (e.g., connected to the inverting feedback node in a follower circuit). Clean all solder flux residue thoroughly, or use PTFE standoffs and air wiring for extreme electrometer applications.

Official Documentation & Cited Datasheets

Primary semiconductor vendor datasheets, errata, and application notes.

DATASHEETTexas Instruments

LMC648x CMOS Rail-to-Rail Input and Output Operational Amplifiers (SNOS674J)

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