[{"data":1,"prerenderedAt":706},["ShallowReactive",2],{"schematic:bss138-bidirectional-i2c-level-shifter:en":3},{"schematic":4,"title":19,"shortDescription":22,"proseSource":664,"localizationFallbackIssues":665,"related":666,"confirmations":665},{"schemaVersion":5,"governance":6,"slug":18,"title":19,"cluster":20,"tier":21,"shortDescription":22,"deepTechnicalOverview":23,"theoryOfOperation":24,"keySpecifications":25,"applications":50,"gotchas":55,"formulas":74,"bom":160,"interactiveElements":198,"circuitJson":242,"svg":662,"relatedComponentSlugs":663},"1.0",{"publication":7,"verification":10,"provenance":15},{"status":8,"publishedDate":9},"published","2026-11-03",{"status":11,"verifiedDate":9,"verifiedBy":12,"checklist":13},"verified","Gemini (AI documentary, CAD and hardware-localization review against NXP Semiconductors Application Note AN10441 \u002F Philips Semiconductor AN97055 Rev. 01 June 2007; owner publication authorization; no bench, simulation, independent second review or native-speaker claim)",{"schema":14,"technicalFacts":14,"relationships":14,"sources":14},true,{"sourceUrls":16},[17],"https:\u002F\u002Fwww.nxp.com\u002Fdocs\u002Fen\u002Fapplication-note\u002FAN10441.pdf","bss138-bidirectional-i2c-level-shifter","BSS138 Bidirectional I2C 3.3V to 5V Level Shifter","microcontroller_interfaces","Tier 1","Bidirectional I2C bus voltage level translator interfacing 3.3V and 5V logic domains using two onsemi BSS138 N-channel MOSFETs with pull-up resistors and decoupled supplies.","This bidirectional logic level translator implements the classic NXP Semiconductors AN10441 \u002F Philips Semiconductor AN97055 topology for bidirectional I2C bus translation between a 3.3V low-voltage domain (VDD1) and a 5.0V high-voltage domain (VDD2). The circuit supports both Serial Data (SDA) and Serial Clock (SCL) lines using two discrete N-channel enhancement-mode MOSFETs (Q1 and Q2, onsemi BSS138 in SOT-23). Both MOSFET gates are permanently tied to the lower power rail (+3.3V), while the sources face the 3.3V bus side and the drains face the 5.0V bus side. Discrete pull-up resistors (R1 through R4, 10 kΩ 1%) pull each bus line to its respective power rail in the idle state. The circuit operates autonomously across three states without any directional control signal: when the bus is idle, both sides pull high to their respective rails while VGS = 0V keeps the transistors in cutoff; when a 3.3V device pulls down, VGS rises to +3.3V (exceeding the 1.5V threshold) and turns the transistor on to drag the 5V line low; and when a 5V device pulls down, current flows forward through the transistor intrinsic body diode until the source falls below threshold, triggering full channel conduction to pull the 3.3V side down cleanly. Local 100 nF ceramic bypass capacitors C1 and C2 suppress rail ripple during simultaneous edge transitions.","### 1. Circuit Topology and Gate-Clamped Bias Architecture\nThe circuit operates as a two-channel bidirectional voltage level translator for the open-drain I2C serial bus, interfacing a lower-voltage system section (VDD1 = +3.3 V) with a higher-voltage section (VDD2 = +5.0 V). Each bus line (SDA and SCL) employs a single discrete N-channel enhancement-mode MOSFET (Q1 for SDA, Q2 for SCL). The gates of both MOSFETs are permanently connected to the lower supply voltage VDD1 (+3.3 V). The source terminals connect to the 3.3 V bus side, and the drain terminals connect to the 5.0 V bus side. Pull-up resistors R1 and R2 (10 kΩ) pull the 3.3 V lines to VDD1, while R3 and R4 (10 kΩ) pull the 5.0 V lines to VDD2. Decoupling capacitors C1 and C2 (100 nF X7R ceramic) provide low-impedance high-frequency bypass directly at each supply domain.\n\n### 2. State 1: Idle and High-Impedance Bus Condition (Both Sides HIGH)\nWhen no bus device (master or slave) is driving the bus, the open-drain lines on both sections are held HIGH by their respective pull-up resistors: the 3.3 V lines sit at +3.3 V and the 5.0 V lines sit at +5.0 V. For both transistors Q1 and Q2, the gate is at +3.3 V and the source is at +3.3 V, resulting in a gate-to-source voltage of exactly zero ($V_{GS} = V_G - V_S = 3.3\\text{V} - 3.3\\text{V} = 0\\text{ V}$). Because $V_{GS}$ is far below the threshold voltage ($V_{GS(th)} = 0.8\\dots 1.5\\text{ V}$), the MOSFETs are completely pinched off in cutoff. The higher-voltage 5.0 V section is completely isolated from the lower-voltage 3.3 V section, preventing overvoltage stress or phantom leakage into 3.3 V microcontroller I\u002FO pins.\n\n### 3. State 2: Low-Voltage Device Driving Down (3.3V to 5V LOW Translation)\nWhen an active device on the 3.3 V section asserts a logic LOW, it pulls the source of the MOSFET down toward ground ($V_S \\approx 0\\text{ V}$). Because the gate remains clamped at +3.3 V, the gate-to-source voltage abruptly rises to $V_{GS} = 3.3\\text{V} - 0\\text{V} = 3.3\\text{ V}$, well above the maximum threshold voltage of 1.5 V. The MOSFET turns fully ON, providing a low-resistance conduction channel ($R_{DS(on)} \\le 6.0\\text{ }\\Omega$). Current from the 5.0 V pull-up resistor flows through the conducting channel to ground via the 3.3 V pull-down driver, pulling the drain (5.0 V bus line) down to a matching logic LOW state ($V_{OL2} = V_{OL1} + I_{pull-up} \\cdot R_{DS(on)} \\le 0.4\\text{ V}$).\n\n### 4. State 3: High-Voltage Device Driving Down (5V to 3.3V LOW Translation)\nWhen an active device on the 5.0 V section asserts a logic LOW, it pulls the drain of the MOSFET down toward ground. Initially, the MOSFET channel is non-conducting. However, the intrinsic body diode of the N-channel MOSFET is oriented with its anode at the source (3.3 V side) and its cathode at the drain (5.0 V side). As the drain voltage drops below approximately 2.6 V, the body diode becomes forward-biased and begins conducting, pulling the source down via diode forward drop ($V_S = V_D + V_{SD} \\approx 0.7\\text{ V}$). As the source voltage drops below $3.3\\text{V} - V_{GS(th)} \\approx 1.8\\text{ V}$, $V_{GS}$ exceeds the threshold voltage, and the inversion channel turns ON. Once the channel conducts, it bypasses the forward diode drop, pulling the 3.3 V line cleanly down to a true logic LOW state matching the 5.0 V driver level.\n\n### 5. State 4: Bus Release and Passive Pull-Up Rise Time Dynamics\nWhen the active pull-down driver on either side releases the bus, both sides begin rising toward their respective supply rails. Initially, while the line voltage is below $V_{DD1} - V_{GS(th)}$, the conducting MOSFET keeps both sides tied together, rising in unison. Once the lower-voltage line exceeds $V_{DD1} - V_{GS(th)} \\approx 1.8\\text{ V}$, $V_{GS}$ falls below the threshold, and the MOSFET turns OFF. From that instant forward, the two bus sections rise independently: the 3.3 V section charges through R1\u002FR2 with time constant $\\tau_1 = R_p \\cdot C_{b1}$, and the 5.0 V section charges through R3\u002FR4 with time constant $\\tau_2 = R_p \\cdot C_{b2}$. This allows high-voltage bus capacitance to be electrically decoupled from the low-voltage bus section, improving overall signal integrity.",[26,29,32,35,38,41,44,47],{"label":27,"value":28},"Low-Voltage Supply (VDD1)","+3.3 V DC nominal (+1.65 V to +3.6 V operating range)",{"label":30,"value":31},"High-Voltage Supply (VDD2)","+5.0 V DC nominal (+2.7 V to +5.5 V operating range)",{"label":33,"value":34},"Supported Bus Protocols","I2C Standard-mode (100 kHz), Fast-mode (400 kHz), SMBus, 1-Wire",{"label":36,"value":37},"Pull-Up Resistors (R1, R2, R3, R4)","10 kΩ 1% standard (scale down to 2.2 kΩ for high bus capacitance)",{"label":39,"value":40},"MOSFET On-Resistance (RDS(on))","≤ 3.5 Ω at VGS = 10 V, ≤ 6.0 Ω at VGS = 4.5 V (onsemi BSS138)",{"label":42,"value":43},"Gate Threshold Voltage (VGS(th))","0.8 V minimum to 1.5 V maximum (onsemi BSS138)",{"label":45,"value":46},"Supply Decoupling (C1, C2)","100 nF 25V X7R ceramic MLCC per supply domain",{"label":48,"value":49},"Low-Level Output Voltage (VOL)","≤ 0.40 V (compliant with I2C Fast-mode specification)",[51,52,53,54],"Interfacing 3.3V microcontrollers (ARM Cortex, ESP32, RP2040) with legacy 5.0V I2C peripherals and sensors","Bidirectional open-drain logic level translation for SMBus, PMBus, and 1-Wire communication links","Core translation circuit for modular breakout boards (SparkFun BOB-12009, Adafruit 757, Pololu 2595)","Galvanically referenced mixed-voltage bus isolation preventing 5.0V overvoltage stress on 3.3V silicon",[56,61,66,70],{"title":57,"trap":58,"solution":59,"severity":60},"Inverted Source-Drain Orientation and Body Diode Conduction","Connecting the MOSFET Drain to the lower-voltage 3.3V rail and Source to the higher-voltage 5.0V rail inverts the intrinsic substrate body diode. The body diode anode (now at 5V) permanently conducts forward into the 3.3V supply rail, causing severe transistor overheating and back-powering the 3.3V microcontroller rail to destructive overvoltage levels.","Always connect the MOSFET Source to the lower-voltage domain (3.3V) and the Drain to the higher-voltage domain (5.0V). Verify that the intrinsic body diode cathode faces the 5.0V side.","critical",{"title":62,"trap":63,"solution":64,"severity":65},"Excessive Bus Capacitance and Slow Rise Time Violations","Standard 10 kΩ pull-up resistors form an RC low-pass filter with bus parasitic capacitance (trace capacitance, cable length, device pin capacitances). When total bus capacitance exceeds 100 pF, the rise time exceeds the 300 ns maximum limit specified by the I2C Fast-mode standard (400 kHz), resulting in bus framing errors and missing ACK bits.","Calculate pull-up resistance using the rise time equation Rp \u003C= tr \u002F (0.8473 * Cb). For 400 kHz Fast-mode operation with multiple slaves, replace 10 kΩ pull-ups with 2.2 kΩ or 4.7 kΩ resistors.","warning",{"title":67,"trap":68,"solution":69,"severity":60},"Insufficient Gate Overdrive at Sub-3.3V Logic Levels","Attempting to use this discrete BSS138 circuit with ultra-low-voltage logic rails (1.8V or 1.2V) fails because the BSS138 gate threshold voltage VGS(th) can be as high as 1.5V. At VDD1 = 1.8V, the effective gate overdrive voltage (VGS - VGS(th)) is only 0.3V, causing high on-resistance (tens of ohms) that violates the I2C VOL maximum specification (0.4V).","For 1.8V to 3.3V or 1.8V to 5.0V level translation, select specialized sub-logic MOSFETs with guaranteed VGS(th) \u003C= 0.8V and low RDS(on) at 1.8V gate drive (such as DMN2004K or SSM3K339R), or use dedicated auto-direction level translators (such as TI TXS0102).",{"title":71,"trap":72,"solution":73,"severity":65},"Missing Common Ground Reference Between Power Domains","Operating the 3.3V and 5.0V sections from separate power supplies without bonding their 0V ground lines allows floating common-mode potential differences. Ground bounce and DC offsets shift the effective gate-source voltage VGS, causing spontaneous bus latch-up, false logic triggers, or gate oxide breakdown.","Ensure a solid, low-impedance ground return connects the ground planes of both the 3.3V and 5.0V systems directly adjacent to the level-shifter circuit.",[75,95,118,140],{"name":76,"latexOrText":77,"description":78,"variables":79},"Maximum Pull-Up Resistor for I2C Rise Time","R_{p(max)} = \\frac{t_r}{0.8473 \\cdot C_b}","Calculates the maximum permissible pull-up resistance to satisfy I2C bus rise time requirements (tr \u003C= 1000 ns for Standard-mode, tr \u003C= 300 ns for Fast-mode) based on total capacitive bus load Cb.",[80,85,90],{"symbol":81,"name":82,"typicalValue":83,"unit":84},"R_{p(max)}","Maximum pull-up resistance","3.54","kΩ",{"symbol":86,"name":87,"typicalValue":88,"unit":89},"t_r","Maximum allowable bus rise time","300","ns",{"symbol":91,"name":92,"typicalValue":93,"unit":94},"C_b","Total bus capacitance per line","100","pF",{"name":96,"latexOrText":97,"description":98,"variables":99},"Minimum Pull-Up Resistor from Output Sink Limit","R_{p(min)} = \\frac{V_{DD} - V_{OL}}{I_{OL}}","Calculates the lower limit on pull-up resistance to prevent exceeding the maximum open-drain driver sink capability (typically 3 mA for Standard and Fast-mode I2C devices).",[100,104,109,113],{"symbol":101,"name":102,"typicalValue":103,"unit":84},"R_{p(min)}","Minimum pull-up resistance","1.53",{"symbol":105,"name":106,"typicalValue":107,"unit":108},"V_{DD}","Bus supply rail voltage","5.00","V",{"symbol":110,"name":111,"typicalValue":112,"unit":108},"V_{OL}","Maximum low-level output voltage","0.40",{"symbol":114,"name":115,"typicalValue":116,"unit":117},"I_{OL}","Maximum open-drain sink current","3.00","mA",{"name":119,"latexOrText":120,"description":121,"variables":122},"Low-Level Voltage During High-to-Low Translation","V_{OL1} = V_{OL2} + I_{pull-up} \\cdot R_{DS(on)}","Calculates the actual low-level voltage delivered to the 3.3V bus side when a 5V master or slave drives the bus line low through the conducting MOSFET channel.",[123,127,131,135],{"symbol":124,"name":125,"typicalValue":126,"unit":108},"V_{OL1}","Output low voltage on 3.3V bus side","0.12",{"symbol":128,"name":129,"typicalValue":130,"unit":108},"V_{OL2}","Driver low voltage on 5.0V bus side","0.10",{"symbol":132,"name":133,"typicalValue":134,"unit":117},"I_{pull-up}","Pull-up current through 3.3V resistor","0.32",{"symbol":136,"name":137,"typicalValue":138,"unit":139},"R_{DS(on)}","MOSFET on-channel static resistance","6.00","Ω",{"name":141,"latexOrText":142,"description":143,"variables":144},"Gate Overdrive Voltage Margin","V_{GS(drive)} = V_{DD1} - V_{in(LV)} \\ge V_{GS(th)}","Quantifies the gate-to-source overdrive voltage available to turn on the MOSFET channel when the low-voltage side pulls down to ground.",[145,149,152,156],{"symbol":146,"name":147,"typicalValue":148,"unit":108},"V_{GS(drive)}","Available gate-source overdrive","3.30",{"symbol":150,"name":151,"typicalValue":148,"unit":108},"V_{DD1}","Low-voltage supply rail",{"symbol":153,"name":154,"typicalValue":155,"unit":108},"V_{in(LV)}","Low-voltage input drive level","0.00",{"symbol":157,"name":158,"typicalValue":159,"unit":108},"V_{GS(th)}","MOSFET maximum threshold voltage","1.50",[161,170,173,180,183,186,189,195],{"refDes":162,"componentName":163,"value":164,"package":165,"quantity":166,"componentSlug":167,"role":168,"notes":169},"Q1","N-Channel Logic-Level MOSFET","BSS138","SOT-23 (TO-236AB)",1,"bss138","SDA Bidirectional Level Shifter","onsemi BSS138; 50V VDSS, 220mA ID, RDS(on) \u003C= 3.5Ω at 10V, VGS(th) 0.8V to 1.5V",{"refDes":171,"componentName":163,"value":164,"package":165,"quantity":166,"componentSlug":167,"role":172,"notes":169},"Q2","SCL Bidirectional Level Shifter",{"refDes":174,"componentName":175,"value":176,"package":177,"quantity":166,"role":178,"notes":179},"R1","SMD Chip Resistor","10kΩ","0805 SMD","SDA 3.3V Pull-Up Resistor","Yageo RC0805FR-0710KL; 10 kΩ 1% 1\u002F8W thick film",{"refDes":181,"componentName":175,"value":176,"package":177,"quantity":166,"role":182,"notes":179},"R2","SCL 3.3V Pull-Up Resistor",{"refDes":184,"componentName":175,"value":176,"package":177,"quantity":166,"role":185,"notes":179},"R3","SDA 5.0V Pull-Up Resistor",{"refDes":187,"componentName":175,"value":176,"package":177,"quantity":166,"role":188,"notes":179},"R4","SCL 5.0V Pull-Up Resistor",{"refDes":190,"componentName":191,"value":192,"package":177,"quantity":166,"role":193,"notes":194},"C1","Multilayer Ceramic Capacitor","100nF","3.3V Supply Decoupling Capacitor","Murata GRM21BR71E104KA01L; 100 nF 25V X7R ceramic 10%",{"refDes":196,"componentName":191,"value":192,"package":177,"quantity":166,"role":197,"notes":194},"C2","5.0V Supply Decoupling Capacitor",{"Q1":199,"Q2":208,"R1":213,"R2":220,"R3":223,"R4":227,"C1":230,"C2":238},{"refDes":162,"name":200,"value":164,"role":201,"description":202,"componentSlug":167,"footprint":165,"specs":203},"SDA Level Shifter MOSFET","SDA Bidirectional Switch","N-channel logic-level MOSFET interfacing the 3.3V and 5.0V SDA lines with gate tied to 3.3V and source facing the 3.3V side.",{"Drain-Source Breakdown (BVDSS)":204,"Continuous Drain Current (ID)":205,"Static On-Resistance (RDS(on))":206,"Gate Threshold (VGS(th))":207},"50 V","220 mA","≤ 3.5 Ω (10V), ≤ 6.0 Ω (4.5V)","0.8 V to 1.5 V",{"refDes":171,"name":209,"value":164,"role":210,"description":211,"componentSlug":167,"footprint":165,"specs":212},"SCL Level Shifter MOSFET","SCL Bidirectional Switch","N-channel logic-level MOSFET interfacing the 3.3V and 5.0V SCL clock lines with gate tied to 3.3V and source facing the 3.3V side.",{"Drain-Source Breakdown (BVDSS)":204,"Continuous Drain Current (ID)":205,"Static On-Resistance (RDS(on))":206,"Gate Threshold (VGS(th))":207},{"refDes":174,"name":178,"value":176,"role":214,"description":215,"footprint":177,"specs":216},"3.3V Bus Pull-Up","Pulls the low-voltage SDA bus line to +3.3V when all connected drivers are in high-impedance state.",{"Resistance":217,"Tolerance":218,"Power Rating":219},"10 kΩ","1%","0.125 W (1\u002F8W)",{"refDes":181,"name":182,"value":176,"role":214,"description":221,"footprint":177,"specs":222},"Pulls the low-voltage SCL clock line to +3.3V when all connected drivers are in high-impedance state.",{"Resistance":217,"Tolerance":218,"Power Rating":219},{"refDes":184,"name":185,"value":176,"role":224,"description":225,"footprint":177,"specs":226},"5.0V Bus Pull-Up","Pulls the high-voltage SDA bus line to +5.0V when all connected drivers are in high-impedance state.",{"Resistance":217,"Tolerance":218,"Power Rating":219},{"refDes":187,"name":188,"value":176,"role":224,"description":228,"footprint":177,"specs":229},"Pulls the high-voltage SCL clock line to +5.0V when all connected drivers are in high-impedance state.",{"Resistance":217,"Tolerance":218,"Power Rating":219},{"refDes":190,"name":193,"value":192,"role":231,"description":232,"footprint":177,"specs":233},"Low-Voltage Decoupling","High-frequency ceramic bypass capacitor absorbing supply switching transients on the 3.3V power rail.",{"Capacitance":234,"Dielectric":235,"Voltage Rating":236,"Tolerance":237},"100 nF","X7R","25 V","10%",{"refDes":196,"name":197,"value":192,"role":239,"description":240,"footprint":177,"specs":241},"High-Voltage Decoupling","High-frequency ceramic bypass capacitor absorbing supply switching transients on the 5.0V power rail.",{"Capacitance":234,"Dielectric":235,"Voltage Rating":236,"Tolerance":237},{"schemaVersion":243,"id":18,"meta":244,"components":251,"nets":394,"junctions":462,"netLabels":479,"wires":480},"1.5",{"title":245,"locale":246,"grid":247,"source":248},"BSS138 Bidirectional I2C Level Shifter","en",20,{"type":249,"ref":250,"url":17},"datasheet","NXP Semiconductors Application Note AN10441 \u002F Philips Semiconductor AN97055 (Rev. 01, June 2007), Section 2.1 & Figure 1: Level shifting for I2C-bus system.",[252,262,271,279,286,291,296,302,309,314,319,325,330,335,340,348,354,362,370,377,383,388],{"id":253,"symbolId":254,"refDes":255,"position":256,"rotation":259,"properties":260},"comp-p-v33-c1","port.power","P_V33_1",{"x":257,"y":258},560,-40,0,{"value":261},"+3.3V",{"id":263,"symbolId":264,"refDes":190,"position":265,"rotation":268,"properties":269},"comp-c1","capacitor.ceramic",{"x":266,"y":267},600,40,90,{"value":192,"package":270},"0805",{"id":272,"symbolId":273,"refDes":274,"position":275,"rotation":259,"properties":277},"comp-p-gnd-c1","gnd.port","GND1",{"x":257,"y":276},160,{"value":278},"GND",{"id":280,"symbolId":254,"refDes":281,"position":282,"rotation":259,"properties":284},"comp-p-v50-c2","P_V50_1",{"x":283,"y":258},620,{"value":285},"+5.0V",{"id":287,"symbolId":264,"refDes":196,"position":288,"rotation":268,"properties":290},"comp-c2",{"x":289,"y":267},660,{"value":192,"package":270},{"id":292,"symbolId":273,"refDes":293,"position":294,"rotation":259,"properties":295},"comp-p-gnd-c2","GND2",{"x":283,"y":276},{"value":278},{"id":297,"symbolId":254,"refDes":298,"position":299,"rotation":259,"properties":301},"comp-p-v33-r1","P_V33_2",{"x":300,"y":258},180,{"value":261},{"id":303,"symbolId":304,"refDes":174,"position":305,"rotation":268,"properties":307},"comp-r1","resistor.iec",{"x":306,"y":267},220,{"value":308,"package":270,"tolerance":218},"10k",{"id":310,"symbolId":254,"refDes":311,"position":312,"rotation":259,"properties":313},"comp-p-v33-r2","P_V33_3",{"x":306,"y":258},{"value":261},{"id":315,"symbolId":304,"refDes":181,"position":316,"rotation":268,"properties":318},"comp-r2",{"x":317,"y":267},260,{"value":308,"package":270,"tolerance":218},{"id":320,"symbolId":254,"refDes":321,"position":322,"rotation":259,"properties":324},"comp-p-v50-r3","P_V50_2",{"x":323,"y":258},420,{"value":285},{"id":326,"symbolId":304,"refDes":184,"position":327,"rotation":268,"properties":329},"comp-r3",{"x":328,"y":267},460,{"value":308,"package":270,"tolerance":218},{"id":331,"symbolId":254,"refDes":332,"position":333,"rotation":259,"properties":334},"comp-p-v50-r4","P_V50_3",{"x":328,"y":258},{"value":285},{"id":336,"symbolId":304,"refDes":187,"position":337,"rotation":268,"properties":339},"comp-r4",{"x":338,"y":267},500,{"value":308,"package":270,"tolerance":218},{"id":341,"symbolId":342,"refDes":343,"position":344,"rotation":259,"properties":346},"comp-p-sda-lv","port.input","P_SDA_LV",{"x":267,"y":345},140,{"value":347},"SDA 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decoupling for 3.3v\u002F5v mcu control.\n2n2222 \u002F 2n2222a npn bjt relay driver with 1n4007 flyback clamping diode\ndiscrete npn bipolar junction transistor low-side relay driver circuit with 1n4007 flyback suppression diode, base saturation drive, and supply decoupling for 3.3v\u002F5v mcu control.\n2n2222 \u002F 2n2222a npn bjt relay driver with 1n4007 flyback clamping diode\ndiscrete npn bipolar junction transistor low-side relay driver circuit with 1n4007 flyback suppression diode, base saturation drive, and supply decoupling for 3.3v\u002F5v mcu control.\nmicrocontroller_interfaces\nnpn general purpose bipolar transistor\n2n2222a\nq1\ngeneral purpose rectifier \u002F clamp diode\n1n4007\nd1\nsubminiature spdt signal \u002F power relay\ng5v-1-dc12\nk1\nbase current-limiting resistor 1 kω\n1kω\nr1\nbase pull-down bleeder resistor 10 kω\n10kω\nr2\nhigh-frequency ceramic decoupling mlcc\n100nf 50v\nc1\nbulk aluminum electrolytic decoupling\n47µf 25v\nc2",{"slug":684,"cluster":20,"tier":21,"supplyVoltage":685,"voltageSpecification":686,"signalDomain":677,"breadboardFriendly":14,"title":690,"shortDescription":691,"bomCount":692,"formulaCount":693,"search":694},"esp32-auto-reset-flashing-circuit",[670],{"kind":687,"value":688,"label":689},"logic","3.3 V (VDD33 on the DevKitC V4)","Operating Logic Level","ESP32 Auto-Reset & Boot Flashing Circuit","Dual-transistor auto-download circuit driving ESP32 EN and IO0 boot strapping pins via USB-to-UART DTR and RTS lines.",8,3,"esp32 auto-reset and boot circuit (dtr\u002Frts)\nthe two-transistor circuit from espressif development boards that lets esptool, arduino ide and platformio reset an esp32 and start its serial bootloader through the dtr and rts lines of a usb-to-uart bridge, with no buttons pressed.\nesp32 auto-reset & boot flashing circuit\ndual-transistor auto-download circuit driving esp32 en and io0 boot strapping pins via usb-to-uart dtr and rts lines.\nesp32 auto-reset and boot circuit (dtr\u002Frts)\nthe two-transistor circuit from espressif development boards that lets esptool, arduino ide and platformio reset an esp32 and start its serial bootloader through the dtr and rts lines of a usb-to-uart bridge, with no buttons pressed.\nmicrocontroller_interfaces\nnpn small-signal transistor\n2n3904\nq1\nnpn small-signal transistor\n2n3904\nq2\nresistor\n10kω\nr1\nresistor\n10kω\nr2\nresistor\n10kω\nr3\nceramic capacitor\n1µf\nc1\ntactile switch\nboot\nsw1\ntactile switch\nen\nsw2",{"slug":696,"cluster":20,"tier":21,"supplyVoltage":697,"voltageSpecification":699,"signalDomain":702,"breadboardFriendly":14,"title":703,"shortDescription":704,"bomCount":680,"formulaCount":681,"search":705},"irlz44n-logic-level-low-side-switch",[670,671,672,698],"24v",{"kind":674,"value":700,"label":701},"+12.0 V DC nominal (+5.0 V to +50.0 V operating range)","Load Supply Voltage (VLOAD)","mixed","IRLZ44N Logic-Level N-Channel MOSFET Low-Side DC Switch","Discrete 12V\u002F24V low-side DC switch circuit driving high-current inductive and resistive loads with an Infineon IRLZ44NPbF logic-level MOSFET from 3.3V or 5V MCU logic.","irlz44n logic-level n-channel mosfet low-side dc switch\ndiscrete 12v\u002F24v low-side dc switch circuit driving high-current inductive and resistive loads with an infineon irlz44npbf logic-level mosfet from 3.3v or 5v mcu logic.\nirlz44n logic-level n-channel mosfet low-side dc switch\ndiscrete 12v\u002F24v low-side dc switch circuit driving high-current inductive and resistive loads with an infineon irlz44npbf logic-level mosfet from 3.3v or 5v mcu logic.\nirlz44n logic-level n-channel mosfet low-side dc switch\ndiscrete 12v\u002F24v low-side dc switch circuit driving high-current inductive and resistive loads with an infineon irlz44npbf logic-level mosfet from 3.3v or 5v mcu logic.\nmicrocontroller_interfaces\nn-channel logic-level power mosfet\nirlz44npbf\nq1\ngate series damping resistor 100 ω\n100ω\nr1\ngate pull-down resistor 10 kω\n10kω\nr2\ninductive flyback clamp diode\n1n4007\nd1\n12v brushed dc motor\n12v dc motor\nm1\nbulk power decoupling electrolytic capacitor 100 µf\n100µf\nc1\nhigh-frequency ceramic bypass capacitor 100 nf\n100nf\nc2",1793836429158]